Routing layer for mitigating stress in a semiconductor die
AssigneeATI Technologies ULC
InventorsRoden Topacio, Gabriel Wong
Life of this patent
Estimating the term…
Abstract
A routing layer for a semiconductor die is disclosed. The routing layer includes traces interconnecting integrated circuit bond-pads to UBMs. The routing layer is formed on a layer of dielectric material. The routing layer includes conductive traces arranged underneath the UBMs as to absorb stress from solder bumps attached to the UMBs. Traces beneath the UBMs protect parts of the underlying dielectric material proximate the solder bumps, from the stress.
Claims22
A semiconductor die comprising:
- i) an integrated circuit formed on one surface of a piece of semiconductor wafer;
- ii) a plurality of input-output (I/O) pads interconnected to said integrated circuit;
- iii) a routing layer comprising:
- a dielectric layer formed on said one surface;
- and a plurality of conductive traces formed on said dielectric layer, each of said conductive traces extending from one of said I/O pads;
- iv) a plurality of under-bump metallizations (UBMs), each comprising a top surface for attaching a respective one of a plurality of solder bumps;
- wherein at least one of said conductive traces pass beneath a top surface of one of said UBMs, and is geometrically arranged to mechanically reinforce said routing layer proximate said one of said UBMs.
A semiconductor die, comprising:
- i) at least one integrated circuit formed on one surface, and a plurality of input-output (I/O) pads connected to said at least one integrated circuit;
- ii) a routing layer comprising a dielectric layer formed on said surface of said die, and a plurality of conductive traces formed on said dielectric layer, each of said conductive traces extending between one of said I/O pads and one of a plurality of bump-pads formed on said dielectric layer;
- and
- iii) a plurality of solder bumps formed on said bump-pads, for electrically interconnecting said integrated circuit to a substrate;
- wherein at least one of said bump-pads is contained within a circular circumscribing area having a radius greater than or equal to the mean radius of a top surface of a corresponding under-bump metallization (UBM) formed on said each bump-pad, at least some of said conductive traces passing through said circular circumscribing area without contacting a contained bump-pad, to mechanically reinforce said routing layer proximate said contained bump-pad.
A routing layer for a semiconductor die, said routing layer comprising:
- i) a plurality of bump-pads for attaching solder bumps using under-bump metallizations (UBMs);
- ii) a plurality of conductive traces interconnecting corresponding ones of said bump-pads and a plurality of input-output (I/O) pads of an integrated circuit formed on a die;
- at least one of said conductive traces passing proximate one of said bump-pads, to mechanically reinforce said routing layer proximate a corresponding one of said UBMs.
A method of manufacturing a semiconductor die for a die having an integrated circuit (IC) interconnected to a plurality of input-output (I/O) pads, said method comprising:
- i) forming a plurality of conductive traces on a dielectric layer, said traces interconnecting corresponding ones of a plurality of under bump metallization (UBM) contact points and said I/O pads, at least one of said conductive traces passing proximate one of said contact points so as to reinforce said dielectric layer proximate said one of said UBM contact points;
- and
- ii) attaching a plurality of said solder bumps to UBM interconnected with corresponding ones of said UBM.
Dependencies are inferred from the claim text.