Chip package structure and method of making the same
AssigneeHangzhou Silergy Semiconductor Technology LTD
InventorsWei Chen, XiaoChun Tan
Life of this patent
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Abstract
Methods and structures related to packaging a chip are disclosed. In one embodiment, a chip package structure includes: (i) a chip having a plurality of first and second contact pads thereon; (ii) a lead frame having a plurality of pins for external connection to the package structure, where the chip is disposed on the lead frame; (iii) a plurality of first bonding wires for connecting the first contact pads to the lead frame; and (iv) a plurality of second bonding wires for connecting the second contact pads to the plurality of pins on the lead frame.
Claims10
A chip package structure, comprising:
- a) a chip having a plurality of first and second contact pads thereon;
- b) a lead frame having a plurality of pins for external connection to said package structure, wherein said chip is disposed on said lead frame;
- c) a plurality of first bonding wires configured to connect said first contact pads to said lead frame;
- and
- d) a plurality of second bonding wires configured to connect said second contact pads to said plurality of pins on said lead frame.
A method of packaging a chip, the method comprising:
- a) providing a chip to be packaged, said chip comprising a plurality of first and second contact pads thereon;
- b) providing a lead frame, said lead frame comprising a plurality of pins for external connection;
- c) disposing said chip on said lead frame;
- d) providing a plurality of first bonding wires for connecting said plurality of first contact pads directly to said lead frame;
- and
- e) providing a plurality of second bonding wires for connecting said plurality of second contact pads to said plurality of pins on lead frame.
Dependencies are inferred from the claim text.