Forming functionalized carrier structures with coreless packages
AssigneeIntel Corporation
InventorsRavi K. Nalla, John Guzek, Javier Soto Gonzalez, Drew Delaney, Hamid Azimi
Life of this patent
Estimating the term…
Abstract
Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include attaching a die to a carrier material, wherein the carrier material comprises a top layer and a bottom layer separated by an etch stop layer; forming a dielectric material adjacent the die, forming a coreless substrate by building up layers on the dielectric material, and then removing the top layer carrier material and etch stop layer from the bottom layer carrier material.
Claims30
A method comprising;
- forming a cavity in a carrier material, wherein the carrier material comprises a top layer and a bottom layer separated by an etch stop layer;
- attaching a die in the cavity;
- forming a dielectric material adjacent the die and on the carrier material bottom layer;
- forming a coreless substrate by building up layers on the dielectric material;
- and
- removing the carrier material top layer and etch stop layer from the bottom layer of the carrier material.
A method comprising;
- attaching a die to a carrier material, wherein the carrier material comprises a top layer and a bottom layer separated by an etch stop layer;
- forming a dielectric material adjacent the die and on the bottom layer of the carrier material;
- forming die pad interconnect structures in the die area;
- forming vias in a non-die area to connect with the bottom layer carrier material;
- forming a coreless substrate by building up layers on the dielectric material;
- and
- removing the top layer carrier material and etch stop layer from the bottom layer carrier material.
A structure comprising:
- a die embedded in a coreless substrate;
- a dielectric material adjacent the die;
- die pad interconnect structures disposed in a die pad area of the die;
- and
- at least one functionalized carrier structure disposed within the coreless substrate, wherein a top surface of the at least one functionalized carrier structure is coplanar with a top surface of the coreless substrate.
A structure comprising:
- a die embedded in a coreless substrate;
- a dielectric material adjacent the die;
- die pad interconnect structures disposed in a die pad area of the die;
- vias in the coreless substrate disposed in a non-die area that are connected to a functionalized carrier structure, wherein the functionalized carrier structure is disposed within the coreless substrate, and wherein a top surface of the functionalized carrier structure is coplanar with a top surface of the coreless substrate.
Dependencies are inferred from the claim text.