Hybrid orientation inversion mode gaa cmosfet
AssigneeShanghai Institute of Microsystem and Information Technology, Chinese Academy
InventorsDeyuan Xiao, Xi Wang, Miao Zhang, Jing Chen, Zhongying Xue
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AssigneeShanghai Institute of Microsystem and Information Technology, Chinese Academy
InventorsDeyuan Xiao, Xi Wang, Miao Zhang, Jing Chen, Zhongying Xue
Estimating the term…
A hybrid orientation inversion mode GAA (Gate-All-Around) CMOSFET includes a PMOS region having a first channel, an NMOS region having a second channel and a gate region. The first channel and the second channel have a racetrack-shaped cross section and are formed of n-type Si (110) and p-type Si(100), respectively; the surfaces of the first channel and the second channel are substantially surrounded by the gate region; a buried oxide layer is disposed between the PMOS region and the NMOS region and between the PMOS or NMOS region and the Si substrate to isolate them from one another. The device structure according to the prevent invention is quite simple, compact and highly integrated. In an inversion mode, the devices have different orientation channels, the GAA structure with the racetrack-shaped, high-k gate dielectric layer and metal gate, so as to achieve high carrier mobility, and prevent polysilicon gate depletion and short channel effects.
A hybrid orientation inversion mode GAA (Gate-All-Around) CMOSFET (Complementary Metal Oxide Semiconductor Field Effect Transistor) comprising a semiconductor substrate, a PMOS region having a first channel, an NMOS region having a second channel, and a gate region, wherein the NMOS region is disposed above the semiconductor substrate, and the PMOS region is disposed above the NMOS region;
A hybrid orientation inversion mode GAA (Gate-All-Around) CMOSFET (Complementary Metal Oxide Semiconductor Field Effect Transistor) comprising a semiconductor substrate, a PMOS region having a first channel and disposed above the semiconductor substrate, an NMOS region having a second channel and disposed above the PMOS region, and a gate region, wherein the NMOS region and the PMOS region each includes a source region and a drain region located at the two opposite ends of the channel thereof, wherein,
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