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US 2011/0254098 A1Published application
Integrated circuit with replacement metal gates and dual dielectrics
AssigneeInternational Business Machines Corporation
InventorsKeith Kwong Hon Wong, Kangguo Cheng, Dechao Guo, Pranita Kulkarni
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Abstract
A replacement gate structure and method of fabrication are disclosed. The method provides for fabrication of both high performance FET and low leakage FET devices within the same integrated circuit. Low leakage FET devices are fabricated with a hybrid gate dielectric comprised of a low-K dielectric layer and a high-K dielectric layer. High performance FET devices are fabricated with a low-K gate dielectric.
Claims20
A semiconductor structure comprising:
- a plurality of replacement-gate field effect transistors, the plurality of replacement-gate field effect transistors comprising at least a first transistor and a second transistor;
- each transistor further comprising a metal gate, the metal gate comprising sidewalls;
- the first transistor comprising a gate dielectric comprised of a low-K material, and wherein the gate dielectric of the first transistor is disposed underneath the metal gate and also disposed on the sidewalls of the metal gate;
- the second transistor comprising a hybrid gate dielectric comprised of a first layer of low-K dielectric material, and a second layer of high-K dielectric material disposed on the first layer of low-K dielectric material, and wherein the gate dielectric of the second transistor is disposed underneath the metal gate and also disposed on the sidewalls of the metal gate of the second transistor.
1 more element
A method for fabricating a plurality of replacement gate transistors, comprising the steps of
- applying an insulating layer over a semiconductor structure, the semiconductor structure comprising a plurality of horizontal surfaces, a plurality of sidewall surfaces, a plurality of active areas, and a plurality of temporary gate structures disposed over the active areas of a semiconductor substrate, whereby the insulating layer is disposed upon both the horizontal surfaces and the sidewall surfaces;
- removing a portion of the insulating layer, whereby the insulating layer remains only on the sidewall surfaces;
- depositing a nitride liner on the semiconductor substrate, whereby the nitride liner is disposed upon both horizontal surfaces and sidewall surfaces;
- depositing an oxide layer on the nitride liner;
- planarizing the oxide layer, whereby the temporary gate structures are exposed;
- removing the temporary gate structures;
- depositing a low-K dielectric on the semiconductor structure, whereby the low-K dielectric is disposed on both horizontal surfaces and sidewall surfaces;
- removing a portion of the low-K dielectric, whereby the low-K dielectric remains only on the sidewall surfaces, and the portion of the semiconductor substrate covered by a deposited photoresist layer;
- depositing a high-K dielectric on the semiconductor structure, whereby the high-K dielectric is disposed upon both horizontal surfaces and sidewall surfaces;
- depositing a metal layer on the high-K dielectric;
- and
- planarizing the metal layer, whereby the oxide layer is exposed.
9 more elements
Dependencies are inferred from the claim text.