Etsoi cmos architecture with dual backside stressors

A device comprising:

• an ETSOI layer of silicon (Si) having a top surface and a backside surface opposite the top surface;
• a semiconductor device formed on the top surface of the Si layer;
• and
• a stress liner on the backside surface of the Si layer.

A method of fabricating a semiconductor device comprising:

• forming an ETSOI substrate comprising a layer of silicon (Si) on a backside substrate with an insulating layer (BOX) there between;
• forming an n-MOS transistor and a p-MOS transistor on a top surface of the Si layer opposite the backside substrate;
• forming a first tensile stress liner on the n-MOS transistor and a first compressive stress liner on the p-MOS transistor;
• forming dielectric layers and metal interconnect layers on the stress liners;
• bonding a handling substrate to the dielectric and metal interconnect layers;
• removing the backside substrate and BOX;
• forming a second tensile stress liner on the backside of the Si layer under the p-MOS transistor;
• and
• forming a second compressive stress liner on the backside of the Si layer under the n-MOS transistor.