US 2011/0254087 A1Published application

Semiconductor device and a method of manufacturing the same

OwnerTomoyuki MIYAKE, Masatoshi Morikawa +2inventors

InventorsTomoyuki MIYAKE, Masatoshi Morikawa, Yutaka Hoshino, Makoto Hatori

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Abstract

To reduce the size and improve the power added efficiency of an RF power module having an amplifier element composed of a silicon power MOSFET, the on resistance and feedback capacitance, which were conventionally in a trade-off relationship, are reduced simultaneously by forming the structure of an offset drain region existing between a gate electrode and an n+ type drain region of the power MOSFET into a double offset one. More specifically, this is accomplished by adjusting the impurity concentration of an n− type offset drain region, which is closest to the gate electrode, to be relatively low and adjusting the impurity concentration of an n type offset drain region, which is distant from the gate electrode, to be relatively high.

Claims20

Dependent claims

A semiconductor device including a MISFET, comprising:

a semiconductor substrate having a front surface and a rear surface opposite to the front surface;
a semiconductor layer formed over the front surface of the semiconductor substrate;
a gate insulating film of the MISFET formed over the semiconductor layer;
a gate electrode of the MISFET formed over the gate insulating film;
a first impurity region formed in the semiconductor layer and constituting a drain region of the MISFET or a source region of the MISFET;
a second impurity region formed in the semiconductor layer and constituting a drain region of the MISFET or a source region of the MISFET;
and
a rear electrode formed on the rear surface of the semiconductor substrate,
wherein a groove is formed in the semiconductor layer and the semiconductor substrate,
wherein a conductive film is embedded into the groove,
wherein the first impurity region is electrically connected with the rear electrode via the conductive film,
wherein, in a plane view, a shape of the gate electrode is longer in a first direction than in a second direction which is substantially perpendicular to the first direction, and
wherein, in the plane view, a shape of the groove is longer in the first direction than in the second direction.

10 more elements

A semiconductor device including a MISFET, comprising:

a semiconductor substrate structure having a front surface and a rear surface opposite to the front surface;
a gate insulating film of the MISFET formed over the front surface of the semiconductor substrate structure;
a gate electrode of the MISFET formed over the gate insulating film;
a first impurity region formed in the semiconductor substrate structure and constituting a drain region of the MISFET or a source region of the MISFET;
a second impurity region formed in the semiconductor substrate structure and constituting a drain region of the MISFET or a source region of the MISFET;
and
a rear electrode formed on the rear surface of the semiconductor substrate structure,
wherein a groove is formed in the semiconductor substrate structure,
wherein a conductive film is embedded into the groove,
wherein the first impurity region is electrically connected with the rear electrode via the conductive film,
wherein, in a plane view, a shape of the gate electrode is longer in a first direction than in a second direction which is substantially perpendicular to the first direction, and
wherein, in the plane view, a shape of the groove is longer in the first direction than in the second direction.

9 more elements

Dependencies are inferred from the claim text.

Facts

Application: 13/167,850Filed 24 Jun 2011
Priority: JP 2003-3139715 Sep 2003
Published: 20 Oct 2011
Term ends: Not estimatedThe source records don’t support an estimate.

Classification16 codes

H10D 30/0221
Of FETs having insulated gates [IGFET]: having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or…
H10D 30/603
Having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs: having asymmetry in the channel direction, e.g. lateral…
H10D 84/0133
Manufacturing their source or drain regions, e.g. silicided source or drain regions: manufacturing common source or drain regions between multiple…
H10D 84/038
Using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology: using silicon technology, e.g. SiGe

Family

Application10/902,130Continuation · filed 30 Jul 2004
Application11/645,577Continuation · filed 27 Dec 2006
Application12/823,453Continuation · filed 25 Jun 2010
Application13/167,850Continuation
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From the US filing history. Foreign family members aren’t listed.