Semiconductor integrated circuit device having reduced unit cell area and method for manufacturing the same

A semiconductor integrated circuit device comprising:

• a plurality of word lines and a plurality of bit lines which intersect each other;
• and
• a plurality of memory cells connected with the word lines and the bit lines,
• the memory cells comprising
• gate electrodes positioned on the word lines on one sides of crossing regions where the word lines intersect the bit lines;
• bit line contacts positioned on the bit lines on one sides of the crossing regions;
• and
• storage node contacts formed in spaces which are surrounded by the word lines and the bit lines.

A semiconductor integrated circuit device comprising:

• a semiconductor substrate;
• an isolation layer formed in the semiconductor substrate to delimit active regions;
• a plurality of word lines buried in the semiconductor substrate and extending parallel to one another with a predetermined spacing;
• a plurality of bit lines extending parallel to one another on the semiconductor substrate and arranged to intersect the word lines, thereby delimiting a plurality of crossing regions and a plurality of unit memory cells;
• a plurality of storage node contacts respectively formed in the active regions of spaces of the unit memory cells;
• and
• a plurality of bit line contacts formed at bit line forming positions which correspond to one sides of the crossing regions,
• wherein the unit memory cells adjacent to each other with the word lines interposed therebetween, are structured in such a way as to share the corresponding word lines, and bit line contacts of the unit memory cells adjacent to each other with the bit lines interposed therebetween, contact one another in such a way as to share corresponding bit lines,
• wherein any one gate electrode positioned on an even word line is among the word lines is arranged between a pair of gate electrodes positioned on adjoining odd word lines, and
• wherein any one bit line contact positioned on an even bit line among the bit lines is arranged between a pair of bit line contacts positioned on adjoining odd bit lines.

A method for manufacturing a semiconductor integrated circuit device, comprising the steps of:

• forming drain regions in predetermined portions of a semiconductor substrate;
• forming first bit line contacts in the semiconductor substrate in such a way as to contact the drain regions;
• forming word lines in preselected portions of the semiconductor substrate;
• forming source regions by implanting impurities into portions of the semiconductor substrate which correspond to both sides of the word lines and both sides of the first bit line contacts;
• forming selectively second bit line contacts on the first bit line contacts;
• forming bit lines over the second bit line contacts in a direction crossing with the word lines;
• and
• forming storage node contacts over the source regions.

A semiconductor integrated circuit device comprising:

• first to third word lines extending along a first direction;
• first to third bit lines extending along a second direction crossing the first direction;
• a first memory cell formed in a space which is surrounded by the first word line, the second word line, the first bit line and the second bit line;
• a second memory cell formed in a space which is surrounded by is the first word line, the second word line, the second bit line and the third bit line;
• and
• a third memory cell formed in a space which is surrounded by the second word line, the third word line, the first bit line and the second bit line,
• wherein the first memory cell and the third memory cell share the second word line, and
• wherein the first memory cell and the second memory cell share the second bit line.