US 2011/0254080 A1Published application

Tunnel field effect transistor

AssigneeInternational Business Machines Corporation

InventorsBruce B. Doris, Kangguo Cheng, Wilfried E. Haensch, Ali Khakifirooz, Isaac Lauer, Ghavam G. Shahidi

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Abstract

A method for fabricating an FET device characterized as being a tunnel FET (TFET) device is disclosed. The method includes processing a gate-stack, and processing the adjoining source and drain junctions, which are of a first conductivity type. A hardmask is formed covering the gate-stack and the junctions. A tilted angle ion implantation is performed which is received by a first portion of the hardmask, and it is not received by a second portion of the hardmask due to the shadowing of the gate-stack. The implanted portion of the hardmask is removed and one of the junctions is exposed. The junction is etched away, and a new junction, typically in-situ doped to a second conductivity type, is epitaxially grown into its place. A device characterized as being an asymmetrical TFET is also disclosed. The source and drain junctions of the TFET are of different conductivity types, and the TFET also includes spacer formations in a manner that the spacer formation on one side of the gate-stack is thinner than on the other side of the gate-stack.

Claims21

Dependent claims

A method for fabricating an FET device, said method comprising:

processing a gate-stack having a first side and a second side, and processing respectively adjoining first and second junctions, wherein said junctions are of a first conductivity type;
forming a hardmask, which hardmask covers said gate-stack and said junctions;
performing an ion implantation at a tilted angle, wherein a first portion of said hardmask is receiving said ion implantation and a second portion of said hardmask is not receiving said ion implantation due to being shadowed by said gate-stack;
selecting said tilted angle in such manner that said first portion covers said first side and adjoining said first junction, while said second portion covers said second side and adjoining said second junction;
performing a selective etch, wherein said first portion of said hard mask is removed and said second portion of said hardmask remains in place;
removing said first junction by etching, while said second junction is being protected by said second portion of said hardmask;
depositing by selective epitaxy a new junction adjoining said first side, and in-situ doping said new junction to a second conductivity type;
wherein said FET device comprises said gate-stack, said new junction, and said second junction, and wherein said FET device is characterized as being a tunnel FET (TFET) device.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application: 12/760,287Filed 14 Apr 2010
Published: 20 Oct 2011
Term ends: Not estimatedThe source records don’t support an estimate.

Classification8 codes

H10P 30/222
Into semiconductor materials, e.g. for doping: characterised by the angle between the ion beam and the crystal planes or the main crystal surface
H10D 30/0221
Of FETs having insulated gates [IGFET]: having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or…
H10D 30/60
Field-effect transistors [FET]: insulated-gate field-effect transistors [IGFET]
H10D 62/021
Manufacture or treatment: forming source or drain recesses by etching e.g. recessing by etching and then refilling