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US 2011/0254072 A1Published application
Charge storage structures and methods
AssigneeMicron Technology, Inc.
InventorJaydeb Goswami
Life of this patent
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Abstract
Methods, devices, and systems associated with charge storage structures in semiconductor devices are described herein. In one or more embodiments, a method of forming nanodots includes forming at least a portion of a charge storage structure over a material by reacting a single-source precursor and a reactant, where the single-source precursor includes a metal and a semiconductor.
Claims33
A method of forming a charge storage structure, comprising:
- forming at least a portion of a charge storage structure over a material by reacting a single-source precursor and a reactant, where the single-source precursor includes a metal and a semiconductor.
A method of forming a charge storage structure, comprising:
- providing a reactant to a reactor;
- providing a single-source precursor to the reactor, where the single-source precursor includes a metal, silicon, a first organic ligand, and a second organic ligand;
- and
- reacting the reactant and the single-source precursor to form metal-silicon nanodots on a material.
1 more element
A method of fabricating a memory cell, comprising:
- forming nanodots over a first dielectric material, where the nanodots are formed by reacting a nitrogen containing radical with a single-source precursor of a metal, silicon, a first organic ligand, and a second organic ligand;
- forming a second dielectric material over the nanodots, where the second dielectric material encases the nanodots;
- forming a third dielectric material over the second dielectric material;
- and
- forming a control gate over the third dielectric material.
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A memory cell, comprising:
- a charge storage structure formed of nanodots over a first dielectric material above a channel region, where the nanodots are a compound of metal and silicon, between a control gate and the channel region;
- and
- a second dielectric material between the nanodots and the control gate.
A memory device, comprising:
- an array of memory cells;
- and
- circuitry for control and/or access of the array;
- where at least one memory cell of the array includes:
- a first dielectric material over a semiconductor;
- a number of nanodots over the first dielectric, where the nanodots are a compound including a metal and silicon;
- a second dielectric material over the nanodots;
- and
- a control gate over the second dielectric material.
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Dependencies are inferred from the claim text.