Method and Apparatus for Assigning Thread Priority in a Processor or the Like
AssigneeIntel Corporation
InventorsDavid W. Burns, James D. Allen, Michael D. Upton, Darrell D. Boggs, David J. Sager
Life of this patent
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Abstract
In a multi-threaded processor, thread priority variables are set up in memory. The actual assignment of thread priority is based on the expiration of a thread precedence counter. To further augment, the effectiveness of the thread precedence counters, starting counters are associated with each thread that serve as a multiplier for the value to be used in the thread precedence counter. The value in the starting counters are manipulated so as to prevent one thread from getting undue priority to the resources of the multi-threaded processor.
Claims30
In a multi-threaded processor for at least first and second threads, a method of assigning thread priority comprising:
- assigning priority to said first thread;
- loading a preliminary value to a thread precedence counter;
- and
- assigning priority to said second thread in response to expiration of said thread precedence counter.
In a multi-threaded processor to handle processing of at least first and second threads, a method of assigning thread priority comprising:
- assigning priority to said first thread;
- and
- assigning priority to said second thread in response to one of a plurality of conditions being true, the conditions including
- if processing of said first thread retires an instruction from said first thread;
- and
- if there is not an indication of approaching instruction side starvation for said first thread.
A processor to handle processing of at least first and second threads in parallel, comprising:
- control logic to assign priority to one of said at least first and second threads;
- a thread precedence counter coupled to said control logic wherein priority is assigned to said second thread after said thread precedence counter expires.
A processor to handle processing of at least first and second threads in parallel, comprising:
- control logic to assign priority to said first thread and to assign priority to said second thread in response to one of a plurality of conditions being true, the conditions including
- if processing of said first thread retires an instruction from said first thread;
- and
- if there is not an indication of approaching instruction side starvation for said first thread.
A computer system to handle processing of at least first and second threads in parallel, comprising:
- a memory to store instructions for first and second threads;
- a processor including
- control logic coupled to said memory to assign priority between said first and second threads;
- a thread precedence counter coupled to said control logic wherein priority is assigned to said second thread after said thread precedence counter expires.
A computer system to handle processing of at least first and second threads in parallel, comprising:
- a memory to store instructions for first and second threads;
- a processor including
- control logic to assign priority to said first thread and to assign priority to said second thread in response to one of a plurality of conditions being true, the conditions including
- if processing of said first thread retires an instruction from said first thread;
- and
- if there is not an indication of approaching instruction side starvation for said first thread.
A set of instructions residing in a storage medium, said set of instructions capable of being executed by a processor to handle processing of at least first and second threads in parallel and assign thread priority comprising:
- assigning priority to said first thread;
- loading a preliminary value to a thread precedence counter;
- and
- assigning priority to said second thread after said thread precedence counter expires.
Dependencies are inferred from the claim text.