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US 2011/0239182 A1Published application
Automatic circuit design technique
AssigneeFujitsu Limited
InventorsIzumi Nitta, Yu Liu
Life of this patent
Estimating the term…
Abstract
A set of pareto optimal solutions that are non-dominated solutions in a solution specification space for respective items in requirement specification is extracted with a combination of a circuit configuration including a specific function and a process constraint condition. Furthermore, pareto optimal solutions are extracted for all combinations of the circuit configuration and the process constraint condition, and pareto optimal solutions are extracted for the respective process constraint conditions. When such extracted data is distributed to designers, it is possible to reduce time to generate the pareto optimal solutions, and the designers can design the optimum circuit having a desired function by using such extracted data.
Claims11
A non-transitory computer-readable storage medium storing a pareto data generation program for an automatic circuit design for causing a computer to execute a procedure, the procedure comprising:
- first extracting a circuit configuration having a specific function from a circuit configuration data storage device storing data of a plurality of circuit configurations;
- for each combination of the extracted circuit configuration and a process constraint condition among a plurality of process constraint conditions, which are constraint conditions for manufacturing processes to be commonly used for said plurality of circuit configurations and are stored in a process constraint condition storage device, obtaining simulation results for respective items in requirement specification by circuit simulation, while changing values of respective design variables in the circuit configuration a plurality of times so as to satisfy said process constraint condition and a constraint condition of the extracted circuit configuration;
- second extracting, from said simulation results, pareto optimal solutions that are non-dominated solutions in a solution specification space for said respective items in said requirement specification, and storing pertinent values of said respective design variables and pertinent values of said respective items in said requirement specification for each of the extracted pareto optimal solutions into an individual pareto data storage device in association with a combination of an identifier of the process constraint condition and an identifier of the extracted circuit configuration;
- for each of said process constraint conditions, third extracting second pareto optimal solutions that are non-dominated solutions among all of said pareto optimal solutions stored in said individual pareto data storage device in association with the process constraint condition;
- for each of said process constraint conditions, storing said identifier of said circuit configuration, said pertinent values of said respective design variables and said pertinent values of said respective items in said requirement specification, which correspond to each of said second pareto optimal solutions, into a pareto-per-process data storage device;
- fourth extracting third pareto optimal solutions that are non-dominated solution among all of said pareto optimal solutions stored in said individual pareto data storage device, and
- storing said combination of said identifier of said extracted circuit configuration and said identifier of said process constraint condition, said pertinent values of said respective design variables and said pertinent values of said respective items in said requirement specification, which correspond to each of said third pareto optimal solutions, into an entire pareto data storage data storage device.
4 more elements
A non-transitory computer-readable storage medium storing an automatic circuit design program for causing a computer to execute a procedure, the procedure comprising:
- accepting designation of first optimization or second optimization, wherein said first optimization is optimization for a specific process constraint condition among a plurality of process constraint conditions, which are stored in a process constraint condition storage device and are constraint conditions for manufacturing processes, and said second optimization is optimization for all of said plurality of process constraint conditions;
- accepting an input for requirement specification of a circuit design;
- upon accepting said designation of said first optimization, reading out, as pareto optimal solution data, data for said specific process constraint condition, from a pareto-per-process data storage device storing first sets of an identifier of a circuit configuration, pertinent values of respective design variables and pertinent values of respective items in said requirement specification, wherein each of said first sets corresponds to each of pareto optimal solutions for each of said process constraint conditions;
- upon accepting said designation of said second optimization, reading out, as pareto optimal solution data, data from an entire pareto data storage device storing second sets of a combination of an identifier of a circuit configuration and an identifier of a process constraint condition, pertinent value of respective design variables and pertinent values of respective items in said requirement specification, wherein each of said second sets corresponds to each of pareto optimal solutions for each combination of said process constraint condition and said circuit configuration;
- calculating, as a provisional optimal solution, a point whose distance from a point corresponding to said requirement specification after space conversion of a solution specification space to balance value distribution for said respective items in said requirement specification, is shortest and which is on a pareto curve of second pareto optimal solutions obtained after said space conversion is carried out for pareto optimal solutions included in the read pareto optimal solution data, in said solution specification space after said space conversion;
- extracting a pareto optimal solution close to said provisional optimal solution in said solution specification space after said space conversion, from said second pareto optimal solutions, and identifying circuit configuration for said provisional optimal solution from the extracted pareto optimal solution close to said provisional optimal solution;
- mapping said provisional optimal solution to values of said respective design variables in the identified circuit configuration;
- and
- outputting an identifier of the identified circuit configuration and said values of said respective design variables in the identified circuit configuration, which are obtained by the mapping.
6 more elements
A pareto data generation apparatus for automatic circuit design, comprising:
- a circuit configuration data storage device for storing data of a plurality of circuit configurations;
- a circuit selection means for extracting a circuit configuration having a specific function from said circuit configuration data storage device;
- an individual pareto generation means for carrying out a processing for each combination of the extracted circuit configuration and a process constraint condition among a plurality of process constraint conditions, which are constraint conditions for manufacturing processes to be commonly used for said plurality of circuit configurations and are stored in a process constraint condition storage device,
- wherein said processing includes:
- obtaining simulation results for respective items in requirement specification by circuit simulation, while changing values of respective design variables in the extracted circuit configuration a plurality of times so as to satisfy the process constraint condition and a constraint condition of the extracted circuit configuration;
- extracting, from said simulation results, pareto optimal solutions that are non-dominated solutions in a solution specification space for said respective items in said requirement specification;
- and
- storing values of said respective design variables and pertinent values of said respective items in said requirement specification for each of the extracted pareto optimal solutions into an individual pareto data storage device in association with a combination of an identifier of said process constraint condition and an identifier of the extracted circuit configuration;
- a pareto-per-process generation means for extracting, for each of said process constraint conditions, second pareto optimal solutions that are non-dominated solutions among all of said pareto optimal solutions stored in said individual pareto data storage device in association with the process constraint condition, and to store, for each of said process constraint conditions, an identifier of said circuit configuration, said pertinent values of said respective design variables and said pertinent values of said respective items in said requirement specification, which correspond to each of said second pareto optimal solutions, into a pareto-per-process data storage device;
- and
- an entire pareto data generation means for extracting third pareto optimal solutions that are non-dominated solution among all of said pareto optimal solutions stored in said individual pareto data storage device, and to store said combination of said identifier of the extracted circuit configuration and said identifier of said process constraint condition, said pertinent values of said respective design variables and said pertinent values of said respective items in said requirement specification, which correspond to each of said third pareto optimal solutions, into an entire pareto data storage data storage device.
8 more elements
A pareto data generation apparatus for automatic circuit design, comprising:
- a circuit configuration data storage device for storing data of a plurality of circuit configurations;
- and
- a processor executing an operation, the operation comprising:
- extracting a circuit configuration having a specific function from said circuit configuration data storage device;
- carrying out a processing for each combination of the extracted circuit configuration and a process constraint condition among a plurality of process constraint conditions, which are constraint conditions for manufacturing processes to be commonly used for said plurality of circuit configurations and are stored in a process constraint condition storage device, wherein said processing includes:
- obtaining simulation results for respective items in requirement specification by circuit simulation, while changing values of respective design variables in the extracted circuit configuration a plurality of times so as to satisfy the process constraint condition and a constraint condition of the extracted circuit configuration;
- extracting, from said simulation results, pareto optimal solutions that are non-dominated solutions in a solution specification space for said respective items in said requirement specification;
- and
- storing values of said respective design variables and pertinent values of said respective items in said requirement specification for each of the extracted pareto optimal solutions into an individual pareto data storage device in association with a combination of an identifier of said process constraint condition and an identifier of the extracted circuit configuration;
- extracting, for each of said process constraint conditions, second pareto optimal solutions that are non-dominated solutions among all of said pareto optimal solutions stored in said individual pareto data storage device in association with the process constraint condition, and to store, for each of said process constraint conditions, an identifier of said circuit configuration, said pertinent values of said respective design variables and said pertinent values of said respective items in said requirement specification, which correspond to each of said second pareto optimal solutions, into a pareto-per-process data storage device;
- and
- extracting third pareto optimal solutions that are non-dominated solution among all of said pareto optimal solutions stored in said individual pareto data storage device, and to store said combination of said identifier of the extracted circuit configuration and said identifier of said process constraint condition, said pertinent values of said respective design variables and said pertinent values of said respective items in said requirement specification, which correspond to each of said third pareto optimal solutions, into an entire pareto data storage data storage device.
9 more elements
An automatic circuit design apparatus, comprising:
- a process constraint condition storage device for storing a plurality of process constraint conditions, which are constraint conditions for manufacturing processes;
- an input means for accepting designation of first optimization or second optimization, wherein said first optimization is optimization for a specific process constraint condition among said plurality of process constraint conditions stored in said process constraint condition storage device, and said second optimization is optimization for all of said plurality of process constraint conditions, and to accept an input for requirement specification of a circuit design;
- an optimal solution generation means for carrying out a processing comprising:
- upon accepting said designation of said first optimization, reading out, as pareto optimal solution data, data for said specific process constraint condition, from a pareto-per-process data storage device storing first sets of an identifier of a circuit configuration, pertinent values of respective design variables and pertinent values of respective items in said requirement specification, wherein each of said first sets corresponds to each of pareto optimal solutions for each of said process constraint conditions;
- upon accepting said designation of said second optimization, reading out, as pareto optimal solution data, data from an entire pareto data storage device storing second sets of a combination of an identifier of a circuit configuration and an identifier of a process constraint condition, pertinent value of respective design variables and pertinent values of respective items in said requirement specification, wherein each of said second sets corresponds to each of pareto optimal solutions for each combination of said process constraint condition and said circuit configuration;
- calculating, as a provisional optimal solution, a point whose distance from a point corresponding to said requirement specification after space conversion of a solution specification space to balance value distribution for said respective items in said requirement specification, is shortest and which is on a pareto curve of second pareto optimal solutions obtained after said space conversion is carried out for pareto optimal solutions included in the read pareto optimal solution data, in said solution specification space after said space conversion;
- extracting a pareto optimal solution close to said provisional optimal solution in said solution specification space after said space conversion, from said second pareto optimal solutions, and identifying circuit configuration for said provisional optimal solution from the extracted pareto optimal solution close to said provisional optimal solution;
- and
- mapping said provisional optimal solution to values of said respective design variables in the identified circuit configuration;
- and
- an output means for outputting an identifier of the identified circuit configuration and said values of said respective design variables in the identified circuit configuration, which are obtained by the mapping.
8 more elements
An automatic circuit design apparatus, comprising:
- a process constraint condition storage device for storing a plurality of process constraint conditions, which are constraint conditions for manufacturing processes;
- and
- a processor executing an operation, the operation comprising:
- accepting designation of first optimization or second optimization, wherein said first optimization is optimization for a specific process constraint condition among said plurality of process constraint conditions stored in said process constraint condition storage device, and said second optimization is optimization for all of said plurality of process constraint conditions, and to accept an input for requirement specification of a circuit design;
- upon accepting said designation of said first optimization, reading out, as pareto optimal solution data, data for said specific process constraint condition, from a pareto-per-process data storage device storing first sets of an identifier of a circuit configuration, pertinent values of respective design variables and pertinent values of respective items in said requirement specification, wherein each of said first sets corresponds to each of pareto optimal solutions for each of said process constraint conditions;
- upon accepting said designation of said second optimization, reading out, as pareto optimal solution data, data from an entire pareto data storage device storing second sets of a combination of an identifier of a circuit configuration and an identifier of a process constraint condition, pertinent value of respective design variables and pertinent values of respective items in said requirement specification, wherein each of said second sets corresponds to each of pareto optimal solutions for each combination of said process constraint condition and said circuit configuration;
- calculating, as a provisional optimal solution, a point whose distance from a point corresponding to said requirement specification after space conversion of a solution specification space to balance value distribution for said respective items in said requirement specification, is shortest and which is on a pareto curve of second pareto optimal solutions obtained after said space conversion is carried out for pareto optimal solutions included in the read pareto optimal solution data, in said solution specification space after said space conversion;
- extracting a pareto optimal solution close to said provisional optimal solution in said solution specification space after said space conversion, from said second pareto optimal solutions, and identifying circuit configuration for said provisional optimal solution from the extracted pareto optimal solution close to said provisional optimal solution;
- and
- mapping said provisional optimal solution to values of said respective design variables in the identified circuit configuration;
- and
- outputing an identifier of the identified circuit configuration and said values of said respective design variables in the identified circuit configuration, which are obtained by the mapping.
9 more elements
Dependencies are inferred from the claim text.