Method and apparatus for laying out power wiring of semiconductor
AssigneeRenesas Electronics Corporation
InventorMIKIKO SODE
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Abstract
An aspect of the present invention is a method for laying out a power wiring of a semiconductor device. The method includes: modeling the power wiring as an analysis model including a plurality of nodes and a plurality of element resistors provided between the plurality of nodes neighboring each other; obtaining voltage values of the plurality of nodes by a circuit simulation; searching a path of a current flowing into a node of the plurality of nodes when an IR drop violation exists in the voltage values, the node having a maximum value of the IR drop violation; selecting a bottleneck element resistor from among the plurality of element resistors included in the path; and changing a resistance value of the bottleneck element resistor
Claims9
A method for laying out a power wiring of a semiconductor device, the method comprising:
- modeling the power wiring as an analysis model comprising a plurality of nodes and a plurality of element resistors provided between the plurality of nodes neighboring each other;
- obtaining voltage values of the plurality of nodes by a circuit simulation;
- searching a path of a current flowing into a node of the plurality of nodes when an IR drop violation exists in the voltage values, the node having a maximum value of the IR drop violation;
- selecting a bottleneck element resistor from among the plurality of element resistors included in the path;
- and
- changing a resistance value of the bottleneck element resistor.
An apparatus for laying out a power wiring of a semiconductor device, the apparatus comprising:
- a power wiring modeling unit that models the power wiring as an analysis model comprising a plurality of nodes and a plurality of element resistors provided between the plurality of nodes neighboring each other;
- an IR drop determination unit that obtains voltage values of the plurality of nodes and determines whether an IR drop violation exists or not in the voltage values;
- and
- a bottleneck determination unit that searches a path of a current flowing into a node having a maximum value of the IR drop violation from the plurality of nodes, determines a bottleneck element resistor from the plurality of element resistors included in the path, and changes a resistance value of the bottleneck element resistor.
Dependencies are inferred from the claim text.