Layout design apparatus, layout design method, and computer readable medium having a layout design program
AssigneeFujitsu Limited
InventorRyoichi YAMASHITA
Life of this patent
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Abstract
A layout design apparatus that designs a layout of a semiconductor integrated circuit having a plurality of layers, the apparatus includes an extractor configured to extract, when given a lower module used at multiple locations inside an upper module, information regarding upper layer wiring near respective placement locations where the lower module is placed, and a layout design unit configured to lay out the lower module by setting prohibited wiring regions in a layout database based on the upper layer wiring information extracted from multiple locations. The prohibited wiring regions are specific regions that prohibit wiring processes therein, and the layout database is data for laying out the lower module.
Claims12
A layout design apparatus that designs a layout of a semiconductor integrated circuit having a plurality of layers, the apparatus comprising:
- an extractor configured to extract, when given a lower module used at multiple locations inside an upper module, information regarding an upper layer wiring near respective placement locations where the lower module is placed;
- and
- a layout design unit configured to lay out the lower module by setting prohibited wiring region in a layout database based on information regarding the upper layer wiring extracted from the multiple locations, and
- wherein the prohibited wiring regions are specific regions where wiring process is prohibited therein, and
- the layout database is data for laying out the lower module.
A layout design method for designing a layout of a semiconductor integrated circuit having a plurality of layers, the method comprising:
- extracting information regarding an upper layer wiring near respective placement locations where a lower module which is used at multiple locations inside the upper module is placed;
- setting prohibited wiring regions in a layout database based on the information of the upper layer wiring extracted from the multiple locations, the prohibited wiring regions are specific regions that prohibit wiring processes therein, and the layout database is data for laying out the lower module;
- and
- laying out the lower module by using the prohibited wiring regions set in the prohibited wiring region.
A computer-readable recording medium storing a layout design program for designing a layout of a semiconductor integrated circuit having a plurality of layers, the layout design program causing the computer to execute an operation, comprising:
- extracting information regarding an upper layer wiring near respective placement locations where a lower module is placed when the lower module is used at multiple locations inside the upper module;
- setting prohibited wiring regions in a layout database based on information of the upper layer wiring extracted from the multiple locations, and
- wherein the prohibited wiring regions are specific regions that prohibit wiring processes therein, and the layout database is data for laying out the lower module;
- and
- laying out the lower module by using the prohibited wiring regions that have been set.
Dependencies are inferred from the claim text.