Method and apparatus for laying out power wiring of semiconductor device

An apparatus for laying out a power wiring of a semiconductor device comprising an analog circuit and a digital circuit, the apparatus comprising:

• a power wiring modeling unit that models the power wiring as an analysis model comprising a plurality of nodes and a plurality of element resistors provided between the plurality of nodes neighboring each other;
• a substrate noise determination unit that obtains voltage values of the plurality of nodes and determines whether a substrate noise violation exists or not in a voltage value of a node of the analog circuit;
• and
• a bottleneck determination unit that searches, from nodes of the digital circuit, a maximum current node having a maximum amount of current flowing into the node of the analog circuit, determines a bottleneck element resistor from the plurality of element resistors included in a path of a current flowing into the maximum current node, and changes a resistance value of the bottleneck element resistor.