US 2011/0239173 A1 · Common Clock Path Pessimism Analysis for Circuit Designs Using Clock Tree Networks

Abstract

Method, computer program and system to perform timing analysis of designs containing clock networks by eliminating Common Clock Path Pessimism The method includes transforming a clock network into a clock tree that includes nodes with different clock signal arrival times and leaf nodes representing source and destination registers. The tree is populated with information regarding the source and destination registers and the associated timing for the clock arrival signal. The method then enumerates Common Clock Path Pessimism (CCPP) groups, where any source register and any destination register in a CCPP group have the same nearest common ancestor node in the clock tree. The creation of CCPP groups enables analysis time reduction because only one timing calculation is required for the CCPP group instead of having to perform the analysis for each possible pair of registers. The method eliminates CCPP for each CCPP group and then displays the results.

Claims21

Dependent claims

1-20. (canceled)

A method for performing time analysis of an Integrated Circuit (IC) design, the method comprising:

creating an all source registers (ASR) list for each node of a clock tree, wherein the ASR list for each node comprises source registers that are descendants of each node;
creating an all destination registers (ADR) list for each node of the clock tree, wherein the ADR list for each node comprises destination registers that are descendants of each node;
eliminating Common Clock Path Pessimism (CCPP) for each node using the ASR list and the ADR list associated with each node, and a difference list for each node that includes nodes in an ADR list of a parent of said each node that are missing in the ADR list for said each node;
and
outputting results after eliminating CCPP, wherein at least one method operation is executed through a processor.

2 more elements

Dependencies are inferred from the claim text.

Common Clock Path Pessimism Analysis for Circuit Designs Using Clock Tree Networks

Life of this patent

Common Clock Path Pessimism Analysis for Circuit Designs Using Clock Tree Networks

Life of this patent

Abstract

Claims21