Code-assisted error-detection technique

The circuit of claim 1, wherein the first type of error affects a number of symbols which is greater than a pre-determined number of symbols in the set of symbols.

The circuit of claim 2, wherein the pre-determined number of symbols is two.

The circuit of claim 1, wherein the second type of error affects a number of symbols which is less than or equal to a pre-determined number of symbols in the set of symbols.

The circuit of claim 4, wherein the pre-determined number of symbols is two.

The circuit of claim 1, wherein the remedial action includes retransmitting the set of symbols to the circuit.

The circuit of claim 1, wherein the second error information includes a cyclic-redundancy-check code.

The circuit of claim 1, wherein the transmit circuit is to provide a symbol to the other circuit that indicates when the first error information and the second error information are provided by the transmit circuit.

The circuit of claim 1, wherein the set of symbols are encoded using an N-symbol-to-M-symbol encoding technique;

• wherein the decoder circuit decodes the set of symbols in accordance with the N-symbol-to-M-symbol encoding technique;
• and
• wherein the first error information indicates the first type of error in the set of symbols if the set of symbol corresponds to an invalid codeword according to the N-symbol-to-M-symbol encoding technique.

The circuit of claim 10, wherein the receive circuit is to receive, from the other circuit, third error information if another type of error occurred in the received encoded set of symbols;

• wherein the type of error is different from the other type of error;
• and
• wherein the control logic is to perform remedial action if the other type of error occurred during communication of the encoded set of symbols to the other circuit.

The circuit of claim 11, wherein the other type of error affects a number of symbols which is greater than a pre-determined number of symbols in the encoded set of symbols.

The circuit of claim 12, wherein the pre-determined number of symbols is two.

The circuit of claim 10, wherein the type of error affects a number of symbols which is less than or equal to a pre-determined number of symbols in the encoded set of symbols.

The circuit of claim 14, wherein the pre-determined number of symbols is two.

The circuit of claim 10, wherein the remedial action includes retransmitting the encoded set of symbols to the other circuit.

The circuit of claim 10, wherein the error information and the second error information include a cyclic-redundancy-check code.

The circuit of claim 10, wherein the receive circuit is to receive a symbol from the other circuit that indicates when the second error information is provided to the receive circuit.

The circuit of claim 10, wherein, during the DBI encoding technique, symbols in the set of symbols are selectively inverted from a first value to a second value if there are more than a pre-determined number of symbols the set of symbols that have the first value.

The circuit of claim 10, wherein the circuit is a memory controller and the other circuit is a memory device.

The circuit of claim 10, wherein the encoder circuit encodes the set of symbols using an N-symbol-to-M-symbol encoding technique.