Method for enhancing error correction capability of a controller of a memory device without increasing an error correction code engine encoding/decoding bit count, and associated memory device and controller thereof

A memory device, error correction capability thereof being enhanced without increasing an Error Correction Code (ECC) engine encoding/decoding bit count, the memory device comprising:

• a Flash memory comprising a plurality of blocks;
• and
• a controller arranged to access the Flash memory and manage the plurality of blocks, wherein an ECC engine of the controller is implemented by utilizing a microprocessor and/or a control logic within the controller, and the ECC engine comprises:
• a first parity code calculation module, wherein regarding a plurality of rows of a data bit array, the first parity code calculation module respectively calculates a plurality of first parity codes;
• and
• a plurality of second parity code calculation modules, wherein regarding a plurality of sets of columns of the data bit array, the second parity code calculation modules respectively calculate a plurality of second parity codes, wherein each set of the sets comprises two or more of the columns, and the sets do not overlap;
• wherein the ECC engine is arranged to perform encoding/decoding corresponding to the first and the second parity codes.

A controller of a memory device, error correction capability of the controller being enhanced without increasing an Error Correction Code (ECC) engine encoding/decoding bit count, the controller being utilized for accessing a Flash memory within the memory device, the Flash memory comprising a plurality of blocks, the controller comprising:

• a read only memory (ROM) arranged to store a program code;
• and
• a microprocessor arranged to execute the program code to control the access to the Flash memory and manage the plurality of blocks;
• wherein an ECC engine of the controller is implemented by utilizing a control logic within the controller and/or by utilizing the microprocessor executing the program code, and the ECC engine comprises:
• a first parity code calculation module, wherein regarding a plurality of rows of a data bit array, the first parity code calculation module respectively calculates a plurality of first parity codes;
• and
• a plurality of second parity code calculation modules, wherein regarding a plurality of sets of columns of the data bit array, the second parity code calculation modules respectively calculate a plurality of second parity codes, wherein each set of the sets comprises two or more of the columns, and the sets do not overlap;
• wherein the ECC engine is arranged to perform encoding/decoding corresponding to the first and the second parity codes.