US 2011/0239069 A1Published application

Sequential digital circuitry with test scan

AssigneeFreescale Semiconductor, Inc.

InventorsRavindraraj Ramaraju, Prashant U. Kenkare, Gray A. Mussemann, Mihir S. Sabnis

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Abstract

A digital scan chain system having test scan has a plurality of flip-flop modules, each of the plurality of flip-flop modules having a first data bit input, a second data bit input, a test bit input, a clock input, a first data bit output, a second data bit output, and a test bit output. The test bit output of a first flip-flop module is directly connected to the test bit input of a second flip-flop module with no intervening circuitry. First and second multiplexed master/slave flip-flops are directly serially connected. A clocked latch is coupled to the output of the second multiplexed master/slave flip-flop and provides the test bit output. The clocked latch is clocked only during a test mode to save power.

Claims20

Dependent claims

A digital scan chain system having test scan comprising:

a plurality of flip-flop modules, each of the plurality of flip-flop modules having a first data bit input, a second data bit input, a test bit input, a clock input, a first data bit output, a second data bit output, and a test bit output, wherein the test bit output of a first flip-flop module is directly connected to the test bit input of a second flip-flop module with no intervening circuitry, each of the plurality of flip-flop modules comprising:
a first multiplexed master/slave flip-flop for multiplexing between the first data bit input and the test bit input and having an output for providing the first data bit output;
a second multiplexed master/slave flip-flop for multiplexing between the second data bit input and the output of the first multiplexed master/slave flip-flop and having an output for providing the second data bit output;
a latch having an input coupled to the output of the second multiplexed master/slave flip-flop, an output for providing the test bit output and a clock input;
and
a logic gate having a first input for receiving a clock signal, a second input for receiving a test enable signal, and an output coupled to the clock input of the latch for selectively clocking the latch only during a test mode.

3 more elements

A digital scan chain system having test scan comprising:

a plurality of flip-flop modules, each of the plurality of flip-flop modules having a first data bit input, a second data bit input, a test bit input, a clock input, a first data bit output, a second data bit output, and a test bit output, wherein the test bit output of a first flip-flop module is directly connected to the test bit input of a second flip-flop module with no intervening circuitry, each of the plurality of flip-flop modules comprising:
a first multiplexed master/slave flip-flop for multiplexing between the first data bit input and the test bit input and having a first output for providing the first data bit output;
a second multiplexed master/slave flip-flop for multiplexing between the second data bit input and the second data bit output of the first multiplexed master/slave flip-flop, and having a first output for providing the second data bit output and a second output;
a latch having an input coupled to the second output of the second multiplexed master/slave flip-flop, an output for providing the test bit output and a clock input;
and
a logic gate having a first input for receiving a clock signal, a second input for receiving a test enable signal, and an output coupled to the clock input of the latch for selectively clocking the latch only during a test mode.

3 more elements

Dependencies are inferred from the claim text.