Tam with scan frame copy register coupled with serial output

An integrated circuit comprising;

• A. core circuitry having scan paths, the scan paths including scan data input leads, scan data output leads, and scan control input leads;
• and
• B. a test access mechanism having:
• i. a serial data input lead;
• ii. a serial data output lead;
• iii. parallel data output leads coupled to the to the scan data input leads;
• iv. parallel data input leads coupled to the scan data output leads;
• v. control output leads coupled to the scan control input leads;
• vi. a clock signal input;
• vii. a functional clock signal input;
• viii. a test/read input;
• ix. a test access mechanism enable input;
• and
• x. a scan frame copy register having an output coupled with the serial data output lead, the scan frame copy register including a stimulus section, a mask section, a command section, and a frame marker section.