Active calibration for high-speed memory devices

A system that calibrates timing for write operations between a memory controller and a memory device, comprising:

• the memory controller;
• the memory device;
• wherein the memory controller is configured to transmit a data signal containing a test data pattern from the memory controller to the memory device within a time gap required to transition from writing data from the memory controller to the memory device to reading data from the memory device to the memory controller;
• receiving circuitry on the memory device configured to use a timing signal to receive the test data pattern at the memory device;
• and
• calibration circuitry on the memory device configured to use the received test data pattern to calibrate a phase relationship between the data signal and the timing signal.

A method for calibrating timing for write operations between a memory controller and a memory device, the method comprising:

• transmitting data from the memory controller to the memory device;
• receiving the data at the memory device;
• sampling the received data using a timing signal to reproduce the transmitted data;
• sampling the received data using a phase-shifted version of the timing signal to produce sampled data;
• computing a phase error indicator based on the reproduced transmitted data and the sampled data;
• and
• transmitting the phase error indicator from the memory controller to the memory device within a time gap required to transition from writing data from the memory controller to the memory device to reading data from the memory device to the memory controller.

A system for calibrating timing for write operations between a memory controller and a memory device, comprising:

• a memory controller;
• a memory device;
• a link coupled between the memory controller and the memory device to transmit data from the memory controller to the memory device;
• receiving circuitry on the memory device configured to receive the data;
• a data sampler within the receiving circuit to sample the received data using a timing signal to reproduce the transmitted data;
• an edge sampler within the receiving circuit to sample the received data using a phase-shifted version of the timing signal to produce a sampled data;
• a controller on the memory device configured to,
• compute a phase error indicator based on the transmitted data and the sampled data, and
• transmit the phase error indicator from the memory controller to the memory device within a time gap required to transition from writing data from the memory controller to the memory device to reading data from the memory device to the memory controller.