Semiconductor device

A semiconductor device comprising:

• a decoder that generates first and second register control signals in response to an external test code signal;
• a first register unit coupled to the decoder, the first register unit receiving the first register control signal from the decoder, the first register unit outputting in series a plurality of test signals in response to the first register control signal;
• and
• a second register unit coupled to the first register unit, the second register unit receiving the first and second register control signals from the decoder, the second register unit receiving in series the plurality of test signals from the first register unit in response to the first register control signal, the second register unit outputting in parallel the plurality of test signals in response to the second register control signal.

A semiconductor device comprising:

• a decoder that activates a test signal of a plurality of test signals;
• a plurality of first registers connected in series to each other, the plurality of first registers being connected in parallel to the decoder, a first register of the plurality of first registers receiving the test signal activated by the decoder, and the plurality of first registers allowing the test signal to be sequentially transferred through the series connection of the plurality of first registers;
• a plurality of second registers connected in series to each other, the plurality of second registers being connected in series to the plurality of first registers, the plurality of second registers allowing the first test signal to be sequentially transferred through the series connection of the plurality of second registers;
• and
• a plurality of control circuits connected in parallel to the plurality of second registers, the plurality of control circuits receiving in parallel the plurality of test signals from the plurality of second registers.