Test circuit for input/output array and method and storage device thereof
AssigneeElite Semiconductor Memory Technology Inc.
InventorMin-Chung Chou
Life of this patent
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Abstract
The invention provides a test circuit for n input/output arrays. Each of the n input/output arrays has M pairs of input/output. The test circuit includes M write drivers and M comparing circuits. The ith write driver provides an ith test signal to the ith inputs of all of the n input/output arrays, and 1≦i≦M. The jth comparing circuit determines if jth output signals of all of the n input/output arrays are the same, and outputs a jth comparing result correspondingly, and 1≦j≦M. The invention also provides a method of testing n input/output arrays. The invention also provides a storage device.
Claims15
A test circuit for n input/output arrays, wherein each of the n input/output arrays has M pairs of input/output, and the test circuit comprising:
- M write drivers, wherein the ith write driver provides an ith test signal to the ith inputs of all of the n input/output arrays, and 1≦i≦M;
- and
- M comparing circuits, wherein the jth comparing circuit determines if jth output signals of all of the n input/output arrays are the same, and outputs a jth comparing result correspondingly, and 1≦j≦M.
A storage device, comprising:
- n input/output arrays, each of the n input/output arrays has M pairs of input/output;
- and
- a test circuit, coupled to the n input/output arrays, comprising:
- M write drivers, wherein the ith write driver provides an ith test signal to the ith inputs of all of the n input/output arrays, and 1≦i≦M;
- and
- M comparing circuits, wherein the jth comparing circuit determines if jth output signals of all of the n input/output arrays are the same, accordingly outputs a jth comparing result, and 1≦j≦M.
A method of testing n input/output arrays, wherein each of the n input/output arrays has M pairs of input/output, and the method comprising:
- providing M write drivers, wherein the ith write driver outputs a test signal to the ith inputs of all of the n input/output arrays, and 1≦i≦M;
- and
- providing M comparing circuits, wherein the jth comparing circuit determines if jth output signals of all of the n input/output arrays are the same, and outputs a jth comparing result correspondingly, and 1≦j≦M.
Dependencies are inferred from the claim text.