Methods and apparatus to improve turbo performance for events handling

A processor comprising:

• a plurality of cores including a first core and a second core, and
• a turbo mode logic to increase an operating frequency of the second core if the first core is in an idle state, wherein increasing the operating frequency of the second core is to use available power capacity of the first core resulting from the first core being in the idle state;
• a first cache coupled to the first core and a second cache coupled to the second core;
• a memory interface logic coupled to the first and second cores;
• a bus interface logic coupled to the first and second cores.