Register Checkpointing for Speculative Modes of Execution in Out-of-Order Processors
AssigneeInternational Business Machines Corporation
InventorsHarold W. Cain, III, Kattamuri Ekanadham, IL Park
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AssigneeInternational Business Machines Corporation
InventorsHarold W. Cain, III, Kattamuri Ekanadham, IL Park
Estimating the term…
A mechanism is provided for generating a checkpoint for a speculatively executed portion of code. The mechanisms identify, during a speculative execution of a portion of code, a register renaming operation occurring to an entry in a register renaming table of the processor. In response to the register renaming operation occurring to the register renaming table, a determination is made as to whether an update to an entry in a hardware-implemented recovery renaming table is to be performed. If so, the entry in the hardware-implemented recovery renaming table is updated. The entry in the recovery renaming table is part of the checkpoint for the speculative execution of the portion of code.
A method, in a data processing system, for generating a checkpoint for a speculatively executed portion of code, comprising:
An apparatus, comprising:
Dependencies are inferred from the claim text.