Instruction fetch apparatus, processor and program counter addition control method

A processor comprising:

• a program counter configured to manage the address of an instruction targeted to be executed in a program in which instructions belonging to a plurality of instruction sequences are placed sequentially;
• a change designation register configured to designate a change of an increment value on said program counter;
• an increment value register configured to hold the changed increment value;
• an addition control section configured such that if said change designation register designates the change of said increment value on said program counter, then said addition control section increments said program counter based on said changed increment value held in said increment value register, said addition control section further incrementing said program counter by an instruction word length if said change designation register does not designate any change of said increment value on said program counter;
• and
• an instruction execution section configured to execute the instruction indicated by said program counter.