Data Reorganization through Hardware-Supported Intermediate Addresses

A computer program product in a computer-readable storage medium of executable code, wherein the executable code, when executed by a computer, directs the computer to perform actions of:

• assembling, within the computer, data from a plurality of non-contiguous addresses in a real address space into a cache line within a cache, wherein the cache line represents a contiguous block of addresses in an intermediate address space;
• translating, in an address translation unit of the computer, an effective address in a virtual address space into an intermediate address in the intermediate address space, wherein the intermediate address space falls within the contiguous block of addresses represented by the cache line;
• and
• performing a memory access operation on the cache line at a location specified by the intermediate address.

A data processing system comprising:

• a main memory;
• a processing unit;
• a memory cache accessible to the processing unit;
• a first address translation unit, responsive to the processing unit's attempts to access memory addresses, which translates a processing-unit-specified effective address in a virtual address space into an intermediate address in an intermediate address space;
• and
• a second address translation unit, wherein the second address translation unit assembles, within the computer, data from a plurality of non-contiguous addresses in the main memory into a cache line within the memory cache for use by the processing unit, wherein the cache line represents a contiguous block of addresses in an intermediate address space.