Method And Apparatus For Supporting Scalable Coherence On Many-Core Products Through Restricted Exposure
AssigneeIntel Corporation
InventorsJoshua B. Fryman, Mohan Rajagopalan, Anwar Ghuloum
Life of this patent
Estimating the term…
Abstract
In one embodiment, a multi-core processor having cores each associated with a cache memory, can operate such that when a first core is to access data owned by a second core present in a cache line associated with the second core, responsive to a request from the first core, cache coherency state information associated with the cache line is not updated. A coherence engine associated with the processor may receive the data access request and determine that the data is of a memory page owned by the first core and convert the data access request to a non-cache coherent request. Other embodiments are described and claimed.
Claims20
An apparatus comprising:
- a processor including a plurality of cores, wherein each core is associated with one of a plurality of cache memories, wherein a first core is to access data owned by a second core present in a cache line of a second cache associated with the second core without coherence processing if a page table associated with a page including the data indicates ownership of the page is restricted to a single core;
- and
- a coherence engine to perform the coherence processing, wherein the coherence engine is to determine if the data is owned by the second core and if so, convert an access request for the data to a non-coherent request.
A system comprising:
- a processor including a plurality of cores, wherein each core is associated with one of a plurality of cache memories, wherein a first core is to access data owned by a second core present in a cache line of a second cache associated with the second core, responsive to a user-level data access instruction of an application from the first core, the user-level data access instruction to cause the data access without affecting cache coherency information associated with the data, based on a priori knowledge of a data access pattern of the application;
- a coherence engine to receive data access requests and to perform communications according to a cache coherency protocol responsive to the requests and cache coherency information, wherein the coherence engine is to determine if the data is owned by the second core and if so, to enable the data access to be performed without update to the cache coherency information or transfer of the cache line including the data;
- and
- a dynamic random access memory (DRAM) coupled to the processor.
An apparatus comprising:
- a multi-core processor including a plurality of cores, wherein each core is associated with one of a plurality of cache memories, wherein a first core is to access data owned by a second core present in a cache line of a second cache associated with the second core, responsive to a data access request from the first core, without updating cache coherency state information associated with the cache line based on an indicator in a page table to indicate that ownership of the data is restricted to a single core;
- and
- a coherence engine to receive the data access request and to determine if the data is of a memory page owned by the second core based on the indicator.
Dependencies are inferred from the claim text.