Nonvolatile semiconductor memory device and driving method
AssigneeSharp Kabushiki Kaisha
InventorsYutaka Ishikawa, Kazuya Ishihara, Yoshiji Ohta
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Abstract
A nonvolatile semiconductor memory device in which a memory cell life can be prolonged while making it possible to perform writing in units of bits. When command information represents writing, a comparing unit 37 compares written data in a target memory cell with write target data to give a comparison result to a write/read control unit 40, when the comparison result represents matching, the write/read control unit 40 does not instruct a decoder unit (51A, 51B, and 53) to perform writing in the target memory cell, and when the comparison result represents mismatching, the write/read control unit 40 instructs the decoder unit to write the write target data in the target memory cell.
Claims13
A nonvolatile semiconductor memory device comprising:
- a memory cell array having a first sub-bank in which a plurality of nonvolatile memory cells are arranged in a form of a matrix, first terminals of the memory cells of the same row are connected to a common word line, and second terminals of the memory cells of the same column are connected to a common bit line and a second sub-bank having the same configuration as that of the first sub-bank;
- a write/read control unit that performs write or read control for a target memory cell corresponding to a designated address;
- a decoder unit that applies a voltage to the bit line and the word line based on an instruction from the write/read control unit to apply a write voltage or a read voltage to the target memory cell;
- a read circuit that reads written data from the target memory cell to which the read voltage is applied;
- and
- a comparing unit that compares a plurality of data to be input, wherein,
- when respectively designated write target data are written in the plurality of target memory cells located in the first-sub-bank and the second sub-bank, the decoder unit executes, in the same time zone,
- a first operation in which a read voltage is applied to a first target memory cell in the first sub-bank, and
- a second operation in which a write voltage is applied to a second target memory cell only when a comparison result between the written data of the second target memory cell in the second sub-bank and the write target data to the second target memory cell by the comparing unit represents mismatching.
A method of driving a nonvolatile semiconductor memory device including a memory cell array having a first sub-bank in which a plurality of nonvolatile memory cells are arranged in a form of a matrix, first terminals of the memory cells of the same row are connected to a common word line, and second terminals of the memory cells of the same column are connected to a common bit line, and a second sub-bank having the same configuration as that of the first sub-bank, wherein
- when respectively designated write target data are written in the plurality of target memory cells located in the first-sub-bank and the second sub-bank,
- a first operation in which a read voltage is applied to a first target memory cell in the first sub-bank, and a second operation in which a write voltage is applied to a second target memory cell only when a comparison result between written data of the second target memory cell in the second sub-bank and the write target data to the second target memory cell represents mismatching are executed in the same time zone.
A nonvolatile semiconductor memory device comprising:
- a memory cell array having a first sub-bank in which a plurality of memory cells are arranged in a form of a matrix, first terminals of the memory cells of the same row are connected to a common word line, and second terminals of the memory cells of the same column are connected to a common bit line and a second sub-bank having the same configuration as that of the first sub-bank;
- a write/read control unit that performs write or read control for a target memory cell corresponding to a designated address;
- a decoder unit that performs a write process or a read process in the target memory cell based on an instruction from the write/read control unit;
- a read circuit that reads written data from the target memory cell;
- and
- a comparing unit that compares a plurality of data to be input, wherein,
- when respectively designated write target data are written in the plurality of target memory cells located in the first-sub-bank and the second sub-bank,
- the decoder unit executes, in the same time zone
- a first operation in which a read process is performed in a first target memory cell in the first sub-bank and
- a second operation in which a write process is performed in a second target memory cell only when a comparison result between the written data of the second target memory cell in the second sub-bank and the write target data to the second target memory cell by the comparing unit represents mismatching.
Dependencies are inferred from the claim text.