US 2011/0237950 A1Published application

Method and apparatus for multi-beam beamformer based on real-time calculation of time delay and pipeline design

AssigneeShenzhen Landwind Industry Co., Ltd.

InventorGuohai MENG

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Abstract

A multi-beamforming method based on real-time calculation of delay parameter and pipeline technique and an apparatus there of are disclosed. The system separates the parameters that should be calculated in real time from the parameters that does not require real-time calculation, and separates the parameters related to the beam sequencing number and the parameters that are independent of the beam sequencing number, and provides a real-time delay calculation unit that is adapted to different types of probe by means of simple switching. The calculation unit utilizes the pipeline design, the delay parameters of M number of beams are calculated in the calculation unit in pipeline manner, and then the memory of the same channel echo data is read, so that the delay of the beams is realized. The consumption of the FPGA resource is greatly reduced. The present invention enables high delay precision through direct calculation. In order to reduce the occupation of the hardware resource, the present invention uses the pipeline design to allow M number of beams to share the delay parameter calculation unit. The occupation of the hardware resource is greatly reduced accordingly.

Claims8

Dependent claims

A multi-beamforming method based on real-time calculation of delay parameter and pipeline technique, wherein at least one multi-beamforming apparatus is used, each multi-beamforming apparatus receives a channel ultrasound echo, each channel ultrasound echo has M number of wave beams with different angles or scanning positions, the method comprises the following steps:

A. each multi-beamforming apparatus processes one channel echo signal and generates delayed signals for M number of scan lines with different scan angles or positions;
B. the echo signal is linearly written into a dual-port or tri-port RAM by each multi-beamforming apparatus;
C. delay parameters for the M number of wave beams in the same channel are calculated by time-division calculation according to array element parameters related to current channel and focus position parameters, and converted into read addresses of the RAM;
D. within one write cycle, echo data is read out from the RAM in turn according to the read addresses to generate M number of delayed signal outputs;
E. the M number of delayed signal outputs generated in the same channel are transmitted to an interpolation unit and a weighing unit in time division manner for performing fine delay and apodization operation;
F. first beams generated by all multi-beamforming apparatus are superposed to obtain a first synthesized beam,
second beams generated by all multi-beamforming apparatus are superposed to obtain a second synthesized beam,
. . .
Mth beams generated by all multi-beamforming apparatus are superposed to obtain a Mth synthesized beam,
the above operations are done in the same summing unit in time-division and pipeline manner;
G. the outputted M number of beam signals are transferred to the next stage summing unit in time division multiplexing manner to perform the final summing between chips or performed with signal processing and image processing.

8 more elements

A multi-beamforming apparatus based on real-time calculation of delay parameter and pipeline technique, comprising:

an analog frontend that receives echo signal, the analog frontend being connected in sequence to an analog-to-digital conversion module, a DC cancellation module, a write control module, a dual-port or tri-port RAM, an interpolation and weighting unit in pipeline manner and a summing unit in pipeline manner;
wherein the multi-beamforming system further comprises a real-time calculation unit of delay parameter in pipeline manner, the real-time calculation unit receives inputted parameters of M number of beams and calculates corresponding delay parameters that are then converted into read addresses of the RAM, the real-time calculation unit is connected in sequence to an address calculation unit, a propagation counter and a read control module, the read control module is connected to the RAM and the interpolation and weighting unit in pipeline manner to control the reading out of the echo signal.

Dependencies are inferred from the claim text.