Method for exposing through-base wafer vias for fabrication of stacked devices
AssigneeDuPont Air Products NanoMaterials LLC
InventorsHyoung Sik Kim, Jung Hee Lee, Daniel Hernandez Castillo, II, James Matthew Henry
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Abstract
An effective method for forming through-base wafer vias for the fabrication of stacked devices, such as electronic devices, is described. The base wafer can be a silicon wafer, in which case the method relates to TSV (through-silicon via) technology. The method affords high removal rates of silicon under appropriate conditions.
Claims17
A method for preparing a base wafer for constructing an assembly comprising at least two stacked integrated circuit chips at least one of which is from the base wafer, said method comprising:
- a) providing a first base wafer having front and back sides, wherein the front side comprises integrated circuits disposed thereon and is attached to a rotatable polishing head, and wherein the base wafer comprises at least one conductive via comprising conductive metal and extending from the front of the base wafer at least partially through the base wafer;
- b) contacting the back side of the base wafer with a polishing pad and a CMP slurry, said polishing pad being rotatable, the rotation of the head and the pad resulting in abrasive action of the slurry between the wafer and the polishing pad, and
- c) polishing the backside of the base wafer until at least one conductive via extending from the back side of the wafer is exposed or further exposed, wherein a down-force is applied of at least 4 psi during polishing, wherein the polishing pad has a hardness of 45 Shore A to about 85 Shore A, wherein the platen and head speed are each independently 18 rpm to 60 rpm, and wherein the slurry comprises a liquid carrier, 0.2% and 6% by weight of a C2-C6 organic diamine, an abrasive, and at least one metal chelating agent.
A method for preparing a base wafer for constructing an assembly comprising at least two integrated circuit chips at least one of which is from the base wafer, said method comprising:
- a) providing a first base wafer having front and back sides, wherein the front side comprises integrated circuits disposed thereon and wherein the base wafer comprises at least one conductive via comprising conductive metal and extending from the front of the base wafer at least partially through the base wafer;
- b) affixing the front side of the base wafer having integrated circuits thereon to a carrier;
- c) contacting the back side of the base wafer with a polishing pad and a first CMP slurry, said first CMP slurry comprising:
- 1) a liquid carrier;
- 2) a C2-C6 organic diamine;
- 3) an abrasive;
- and
- 4) at least one metal chelating agent, and
- polishing the backside of the base wafer until at least one conductive via is exposed or further exposed, wherein the first base wafer is polished using the first CMP slurry at a rate of at least 10,000 angstroms per minute at 6 psi of down-force.
A method for preparing a base wafer for constructing an assembly comprising at least two integrated circuit chips at least one of which is from the base wafer, said method comprising:
- a) providing a first base wafer having front and back sides, wherein the front side comprises integrated circuits disposed thereon and wherein the base wafer comprises at least one conductive via comprising conductive metal and extending from the front of the base wafer at least partially through the base wafer;
- b) contacting the back side of the base wafer with a polishing pad and a CMP slurry, and
- c) polishing the backside of the base wafer until at least one conductive via is exposed or further exposed, wherein a down-force is applied of at least 4 psi during polishing, wherein the polishing pad has a hardness of 45 Shore A to about 85 Shore A, wherein the platen and head speed are each independently 18 rpm to 60 rpm.
Dependencies are inferred from the claim text.