Closed cell configuration to increase channel density for sub-micron planar semiconductor power device
AssigneeAlpha and Omega Semiconductor Incorporated
InventorShekar Mallikararjunaswamy
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Abstract
A semiconductor power device supported on a semiconductor substrate that includes a plurality of transistor cells, each cell has a source and a drain region disposed on opposite sides of a gate region in the semiconductor substrate. A gate electrode is formed as an electrode layer on top of the gate region for controlling an electric current transmitted between the source and the drain regions. The gate electrode layer disposed on top of the semiconductor substrate is patterned into a wave-like shaped stripes for substantially increasing an electric current conduction area between the source and drain regions across the gate.
Claims11
A method for configuring a semiconductor power device supported on a semiconductor substrate comprising:
- forming a plurality of transistor cells each having a source and a drain region disposed on opposite sides of a gate region in said semiconductor substrate;
- and
- forming a gate electrode layer on top of the gate region on top of said gate region for controlling an electric current transmitted between the source and the drain regions and patterning said gate electrode layer into a wave-like shaped stripes for substantially increasing an electric current conduction area between the source and drain regions across the gate.
Dependencies are inferred from the claim text.