Electronic device wafer level scale packages and fabrication methods thereof

A fabrication method for an electronic device chip scale package, comprising:

• providing a semiconductor wafer with a plurality of electronic devices thereon;
• bonding the semiconductor wafer with a supporting substrate and thinning the back of the semiconductor wafer;
• etching the back of the semiconductor wafer to create a first opening;
• conformably depositing an insulating layer on the back of the semiconductor wafer;
• etching the insulating layer at the bottom of the first opening and creating a second opening exposing part of contact pads, the exposed part of the contact pads comprising a vertical portion and a horizontal portion, wherein the second opening extends over upper surfaces of the contact pads, and lower surfaces of the contact pads are between the upper surfaces and the semiconductor wafer;
• after the second opening is created, conformably depositing a conductive layer on the back of the semiconductor wafer and patterning the conductive layer, thereby creating an S-shaped connection constructed by the conductive layer and the contact pads;
• forming exterior connections and terminal contact pads connecting the S-shaped connection;
• and
• forming a dam structure between the semiconductor wafer and the supporting substrate, wherein the second opening extends into the dam structure, and a bottom surface of the second opening is between upper surfaces of the dam structure and the upper surfaces of the contact pads.