Chipstack package and manufacturing method thereof

A chip stack package comprising:

• a package substrate including:
• a first surface, the first surface including at least a first terminal;
• and
• a second surface, the second surface including at least a second terminal, the second terminal being in electrical contact with the first terminal,
• wherein the second terminal is an external terminal of the package;
• and
• a first chip stacked on the package substrate, the first chip including:
• a first surface;
• a second surface;
• at least a first chip pad on the first surface of the first chip;
• at least a first connection via formed through a portion of the first chip and separate from the first chip pad, the first connection via having an upper surface and a lower surface;
• and
• at least a first rerouting line connecting the first chip pad and the first connection via.

A chip stack package comprising:

• a first chip including:
• a first backside surface;
• a first active surface;
• at least a first chip pad on the active surface;
• at least a first connection via formed through a portion of the first chip and separate from the first chip pad, the first connection via having an upper surface and a lower surface, a lower portion of the first connection via extending beyond the first backside surface;
• and
• at least a first rerouting line connecting the first chip pad and the first connection via;
• and
• a second chip stacked on the first chip, the second chip including:
• a second backside surface;
• an second active surface;
• a second chip pad on the active surface;
• a second connection via formed through a portion of the second chip separate from the second chip pad, the second connection via having an upper surface and a lower surface, a lower portion of the first connection via extending beyond the second backside surface;
• and
• a second rerouting line connecting the second chip pad and the second connection via.