Reducing buffer size requirements in an electronic registration system

A system for performing an electronic registration correction, the system comprising:

• a memory storing a page of a digital image comprising a spatially mapped array of large address blocks arranged in row/column format, each of said large address blocks comprising rows of column blocks comprising rows of scanlines comprising a row of pixel locations, wherein each pixel location has an associated address comprising a page address segment identifying a row of large address blocks in said spatially mapped array, a row address segment identifying a row of column blocks within a row of large address blocks, a column address segment identifying a column block within a row of column blocks, a scanline address segment identifying a scanline within said column block, and a pixel address segment identifying a pixel location within said scanline;
• a storage device;
• and
• a processor in communication with said storage device and said memory, said processor executing machine readable instructions for performing the method of:
• receiving an array of total skew errors, each pixel location of each scanline in said spatially mapped having an associated total skew error, a each total skew error in said array comprising a first and second sequence of bits, said first bit sequence containing a measured fine skew, and said second bit sequence containing a measured coarse skew for the column block wherein that pixel resides, each total skew error in said array of total skew errors being addressable as a function of said column address segment and pixel address segment of the address associated with that pixel location;
• selecting a set of large address blocks within a same row of said spatially mapped array and moving said selected large address blocks from page memory into RAM, said set of large address blocks having been selected as a function of a selected pixel within any of said large address blocks using said page address segment of said selected pixel's associated address;
• selecting a set of column blocks within said row of large address blocks which require a coarse skew correction and moving said selected set of column blocks from RAM into FPGA memory, said column blocks having been selected as a function of said selected pixel's row address segment, having moved said column blocks from RAM into FPGA resulting in said blocks in FPGA having been coarse skew corrected by virtue of these column blocks having been selected as a function of coarse skew;
• and
• for each pixel location of each scanline of each row address of each column block in FPGA memory:
• retrieving an amount of measured fine skew for the current pixel for the current scanline within the current column block, said amount of measured fine skew being retrieved from said array of total skew errors using the current pixel location's column address segment and pixel address segment to reference the total skew error for the current pixel location in said array of total skew errors and applying an amount of correction which compensates for said retrieved amount of fine skew error associated with the current pixel;
• and
• generating a raster output line of skew corrected data.

A method for electronic registration correction comprising:

• receiving, in a memory, a page of a digital image comprising a spatially mapped array of large address blocks arranged in row/column format, each of said large address blocks comprising rows of column blocks comprising rows of scanlines comprising a row of pixel locations, wherein each pixel location has an associated address comprising a page address segment identifying a row of large address blocks in said spatially mapped array, a row address segment identifying a row of column blocks within a row of large address blocks, a column address segment identifying a column block within a row of column blocks, a scanline address segment identifying a scanline within said column block, and a pixel address segment identifying a pixel location within said scanline;
• and
• for each column block in said spatially mapped array:
• obtaining, for the current column block, an amount of a measured coarse skew error determined on a per-block basis;
• and
• for each pixel in said current column block:
• obtaining, for the current pixel, an amount of a measured fine skew error determined on a per-pixel basis;
• generating a total skew error comprising a first and second sequence of bits, said first bit sequence containing said measured fine skew error, and said second bit sequence containing said measured coarse skew error for said current block wherein said current pixel resides;
• and
• storing said total skew error in an array of total skew errors, said total skew error for said current pixel being addressable as a function of at least said column address segment and pixel address segment of the address associated with said current pixel.