Implementing enhanced link bandwidth in a headless interconnect chip

A circuit for implementing enhanced link bandwidth for a headless interconnect chip in an interconnect system, the headless interconnect chip not connected to a source device or a destination device;

• said circuit comprising:
• a headless interconnect chip including a cut through switch and a store and forward switch;
• a plurality of links connected to said headless interconnect chip;
• said headless interconnect chip receiving a packet from an incoming link to be transmitted on an outgoing link;
• said headless interconnect chip selectively using the cut through switch and the store and forward switch for moving packets received from the incoming link to an outgoing link on the headless interconnect chip.

A multiple-path local rack interconnect system comprising:

• a plurality of interconnect chips including a source interconnect chip coupled to a source device, a destination interconnect chip coupled to the destination device, and a headless interconnect chip, said headless interconnect chip being an intermediate interconnect chip and said headless interconnect chip not connected to a source device or a destination device;
• a plurality of serial links connected between each of said plurality of interconnect chips;
• each of said interconnect chips including a cut through switch and a store and forward switch;
• said headless interconnect chip receiving a packet from an incoming link to be transmitted on an outgoing link;
• said headless interconnect chip selectively using the cut through switch and the store and forward switch for moving packets received from the incoming link to an outgoing link on the headless interconnect chip.

A design structure embodied in a machine readable medium used in a design process, the design structure comprising:

• a circuit tangibly embodied in the machine readable medium used in the design process, said circuit for implementing enhanced link bandwidth for a headless interconnect chip in an interconnect system, said headless interconnect chip not connected to a source device or a destination device;
• said circuit comprising:
• a headless interconnect chip including a cut through switch and a store and forward switch;
• a plurality of links connected to said headless interconnect chip;
• said headless interconnect chip receiving a packet from an incoming link to be transmitted on an outgoing link;
• said headless interconnect chip selectively using the cut through switch and the store and forward switch for moving packets received from the incoming link to the outgoing link on the headless interconnect chip, wherein the design structure, when read and used in the manufacture of a semiconductor chip produces a chip comprising said circuit.