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US 2011/0235531 A1Published application
Performance And Traffic Aware Heterogeneous Interconnection Network
AssigneeIntel Corporation
InventorsSriram R. Vangal, Nitin Y. Borkar, Zhen Fang
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Abstract
In one embodiment, a method includes comparing an occupancy level of a buffer of a port of a router to a threshold, and controlling the port to operate at a first voltage and frequency based at least in part on the comparison, and at least one other port of the router is controlled to operate at a second voltage and frequency. Other embodiments are described and claimed.
Claims20
A method comprising:
- determining an occupancy level of a first buffer, the first buffer of a first port of a router coupled to a plurality of routers and at least one processor;
- comparing the occupancy level of the first buffer to a first threshold;
- and
- controlling the first port to operate at a first voltage and frequency based at least in part on the comparison, wherein at least one other port of the router is controlled to operate at a second voltage and frequency.
1 more element
An apparatus comprising:
- a router having a plurality of ports each including a plurality of virtual channel buffers coupled in parallel between an input multiplexer and an output multiplexer, wherein each of the plurality of ports is to be individually controlled to operate at a selected frequency-voltage pair.
A system comprising:
- a plurality of processing engines;
- at least one memory controller;
- and
- a plurality of routers to couple the processing engines and the at least one memory controller via an interconnection network, wherein each router includes a plurality of ports each having a plurality of parallel buffers coupled between an input multiplexer and an output multiplexer, a cross bar coupled to the output multiplexer, an output selection logic coupled to the output multiplexer and the cross bar to select a packet from the output multiplexer and a port of another of the plurality of routers to receive the packet, an occupancy monitoring logic coupled to the plurality of parallel buffers to determine an occupancy level of each of the plurality of parallel buffers and to compare the corresponding occupancy level to a threshold to generate a result, and a controller to receive the result, a global clock signal and a voltage signal and to provide a frequency-voltage pair for each of the plurality of parallel buffers based at least in part on the result, wherein each parallel buffer can operate at a heterogeneous frequency-voltage pair, and the plurality of processing engines, the at least one memory controller, and the plurality of routers are configured on a single semiconductor die.
1 more element
Dependencies are inferred from the claim text.