Clock-forwarding low-power signaling system

An integrated circuit device comprising:

• an open-loop clock distribution circuit to generate a transmit clock signal in response to an externally-supplied clock signal;
• a transmit circuit to output a data signal onto a first external signal line in response to the transmit clock signal, the transmit clock signal being permitted to drift relative to the externally-supplied clock signal by at least half the period of the transmit clock signal such that the data signal exhibits a corresponding drift relative to the externally-supplied clock signal;
• and
• a multiplexing circuit to select either a write-able data storage or a calibration data source to supply data values to the transmit circuit to be conveyed in the data signal.

A memory controller comprising:

• a receive circuit to receive a data signal from a memory device in response to a receive clock signal;
• clock circuitry to generate a plurality of clock signals, including the receive clock signal and a system clock signal that is output to the memory device to time transmission of the data signal, the system clock signal oscillating at a frequency high enough to provide a respective clock edge for each symbol conveyed in the data signal;
• and
• calibration circuitry to adjust the phase of the receive clock signal frequently enough to compensate for phase drift between the data signal and the system clock signal, the phase drift being uncompensated by the memory device and permitted to extend at least a symbol time.

A method of operation within an integrated circuit device, the method comprising:

• receiving a first clock signal via an external clock signal line;
• generating a transmit clock signal in response to the first clock signal;
• and
• transmitting a data signal onto a first external signal line in response to the transmit clock signal and unaccompanied by a timing reference signal, the transmit clock signal being permitted to drift relative to the first clock signal by at least half the period of the transmit clock signal such that the data signal exhibits a corresponding drift relative to the first clock signal.

A method of operation within a memory system, the method comprising:

• receiving a system clock signal within a memory device;
• generating a transmit clock signal within the memory device in response to the system clock signal;
• outputting a data signal from the memory device onto a first signal line in response to the transmit clock signal, the transmit clock signal being permitted to drift relative to the system clock signal by at least half the period of the transmit clock signal such that the data signal exhibits a corresponding drift relative to the system clock signal;
• generating a receive clock signal within a memory controller;
• receiving the data signal within the memory controller via the first signal line and in response to the receive clock signal;
• and
• adjusting a phase of the receive clock signal based on values conveyed in the data signal to compensate for the drift between the transmit clock signal relative to the system clock signal.

A method of operation within an integrated circuit device, the method comprising:

• receiving a first clock signal via an external clock signal line;
• generating a transmit clock signal in response to the first clock signal;
• transmitting a sequence of data values onto a first external data line in response to the transmit clock signal, the transmit clock signal being permitted to drift relative to the first clock signal by at least half the period of the transmit clock signal such that the data signal exhibits a corresponding drift relative to the first clock signal;
• and
• selecting either a calibration data sequence or data retrieved from a storage array of the memory device to be the transmitted sequence of data values.