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US 2011/0235456 A1Published application
Power supply control circuit and semiconductor apparatus including the same
AssigneeHynix Semiconductor Inc.
InventorSin Hyun JIN
Life of this patent
Estimating the term…
Abstract
A power supply control circuit includes a power supply control unit configured to receive a rank mode signal and generate a plurality of power supply enable signals based on a rank mode designated by the rank mode signal, a chip selection signals and bank address signals; and a plurality of power blocks configured to supply power to a plurality of memory banks of a plurality of chips based on the plurality of power supply enable signals.
Claims20
A power supply control circuit comprising:
- a power supply control unit configured to receive a rank mode signal and generate a plurality of power supply enable signals based on a rank mode designated by the rank mode signal, a chip selection signals and bank address signals;
- and
- a plurality of power blocks configured to supply power to a plurality of memory banks of a plurality of chips based on the plurality of power supply enable signals.
A semiconductor apparatus comprising:
- a plurality of chips stacked vertically and having four memory bank regions which are placed at the same positions in a vertical direction;
- and
- a power supply control circuit configured to supply power to two memory bank regions of the four memory bank regions of the plurality of chips in common in response to bank address signals in a first rank mode, and supply the power to two memory bank regions of the four memory bank regions of the plurality of chips in common in response to chip selection signals in a second rank mode.
A semiconductor apparatus comprising:
- a plurality of chips stacked vertically and having a plurality of memory bank regions placed at the same positions in a vertical direction;
- and
- a power supply control circuit configured to supply power to the plurality of memory bank regions of the plurality of chips based on the rank mode, chip selection signals and bank address signals,
- wherein the plurality of memory bank regions of the plurality of chips are assigned with different bank address signals based on the rank mode.
1 more element
Dependencies are inferred from the claim text.