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US 2011/0235445 A1Published application
Method and system to lower the minimum operating voltage of register files
AssigneeIntel Corporation
InventorsSeung H. Hwang, Sapumal B. Wijeratne
Life of this patent
Estimating the term…
Abstract
A method and system to lower the minimum operating voltage of a register file without increasing the area of each bit cell of the register file. In one embodiment of the invention, the register file is coupled to logic that reduces the contention between the NMOS devices and the PMOS devices in each bit cell of the register file during write and/or read operations of the register file. By doing so, the register file is able to operate at a lower minimum operating voltage.
Claims24
An apparatus comprising:
- a circuit coupled to a plurality of register file bit cells, to lower a minimum operating voltage of the plurality of register file bit cells in response to an input data to the plurality of register file bit cells.
An apparatus comprising:
- a register file having one or more bit cells;
- and
- logic coupled with the register file, to reduce contention between negative-channel metal-oxide-semiconductor field effect transistor (MOSFET) (NMOS) devices and positive-channel MOSFET (PMOS) devices in each bit cell based at least in part on input data signals to the register file.
A method comprising:
- reducing contention between negative-channel metal-oxide-semiconductor field effect transistor (MOSFET) (NMOS) devices and positive-channel MOSFET (PMOS) devices in each bit cell of a register file without increasing an area of each bit cell.
Dependencies are inferred from the claim text.