Nonvolatile semiconductor memory device
AssigneeRenesas Electronics Corporation
InventorYasuaki Watanabe
Life of this patent
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Abstract
A nonvolatile semiconductor memory device includes: a sense amplifier; bit lines coupled to the sense amplifier; memory cell transistors and dummy cell transistors coupled in parallel with the bit lines; and a current generating circuit that supplies a test current to current nodes. Either of the source and the drain of each of the dummy cell transistors is coupled to a bit line and the other is coupled to a current node. In a read operation test, the current generating circuit is activated and then the dummy cell transistors are turned on. The sense amplifier compares the test current passed through a bit line with a reference current and outputs output data corresponding to the result of the comparison.
Claims7
A nonvolatile semiconductor memory device comprising:
- a sense amplifier;
- a bit line coupled to the sense amplifier;
- a memory cell transistor and a dummy cell transistor coupled to the bit line;
- and
- a current generating circuit supplying a test current to a current node,
- wherein either of the source and the drain of the dummy cell transistor is coupled to the bit line and the other is coupled to the current node, and
- wherein in a read operation test,
- after the current generating circuit is activated, the dummy cell transistor is turned on, and
- the sense amplifier compares the test current passed through the bit line with a reference current and outputs output data corresponding to the result of the comparison.
Dependencies are inferred from the claim text.