US 2011/0235437 A1 · Single-Polycrystalline Silicon Electrically Erasable and Programmable Memory Device of Varied Gate Oxide Thickness, Using PIP or MIM Coupling Capacitor for Cell Size Reduction and Simultaneous VPP and VNN for Write Voltage Reduction

Abstract

A single polycrystalline silicon floating gate nonvolatile memory device has a storage MOS transistor and at least one polycrystalline-insulator-polycrystalline (PIP) or metal-insulator-metal (MIM) capacitor manufactured with dimensions that can be fabricated using current low voltage logic integrated circuit process. The PIP or MIM capacitor is a coupling capacitor with a first plate connected to a floating gate of the storage MOS transistor to form a floating gate node. The coupling PIP or MIM capacitor couples the voltage level applied to a second plate of the PIP or MIM capacitor to the floating gate node with a large coupling ratio approximately 90% so as to initiate Fowler-Nordheim tunneling effect for erasing or programming the memory device. The memory device may also have another PIP or MIM capacitor with a first pate connected to the floating gate of the storage MOS transistor for serving as a tunneling capacitor.

Claims90

Dependent claims

A single polycrystalline silicon electrically erasable and programmable floating gate memory device, comprising:

a one-pass PMOS transistor having a drain connected to a bit line and a gate connected to a word line;
a floating gate PMOS storage transistor having a single polycrystalline (single-poly) floating gate, a drain connected a source of said one-pass PMOS transistor and a source connected to a source line;
and
a first polycrystalline-Insulator-polycrystalline (PIP) or metal-insulator-metal (MIM) capacitor, said first PIP or MIM capacitor having a first plate connected to said single-poly floating gate and a second plate connected to a first voltage source node;
wherein said one-pass PMOS transistor and said floating gate PMOS storage transistor are formed in an N-well, and said first PIP or MIM capacitor is a coupling capacitor for coupling a substantial portion of a voltage level applied to said first voltage source node to said single-poly floating gate with a coupling ratio greater than 90%.

2 more elements

A single polycrystalline silicon electrically erasable and programmable floating gate memory device, comprising:

a one-pass NMOS transistor having a drain connected to a bit line and a gate connected to a word line;
a floating gate NMOS storage transistor having a single polycrystalline (single-poly) floating gate, a drain connected a source of said one-pass NMOS transistor and a source connected to a source line;
and
a first polycrystalline-Insulator-polycrystalline (PIP) or metal-insulator-metal (MIM) capacitor, said first PIP or MIM capacitor having a first plate connected to said single-poly floating gate and a second plate connected to a first voltage source node;
wherein said one-pass NMOS transistor and said floating gate NMOS storage transistor are formed in a triple P-well on a deep N-well, and said first PIP or MIM capacitor is a coupling capacitor for coupling a substantial portion of a voltage level applied to said first voltage source node to said single-poly floating gate with a coupling ratio greater than 90%.

2 more elements

A single polycrystalline silicon electrically erasable and programmable floating gate memory device, comprising:

a one-pass NMOS transistor having a drain connected to a bit line and a gate connected to a word line;
a floating gate NMOS storage transistor having a single polycrystalline (single-poly) floating gate, a drain connected a source of said one-pass NMOS transistor and a source connected to a bit line;
and
a first polycrystalline-Insulator-polycrystalline (PIP) or metal-insulator-metal (MIM) capacitor, said first PIP or MIM capacitor having a first plate connected to said single-poly floating gate and a second plate connected to a first voltage source node;
wherein said one-pass NMOS transistor and said floating gate NMOS storage transistor are formed on a P-substrate, and said first PIP or MIM capacitor is a coupling capacitor for coupling a substantial portion of a voltage level applied to said voltage first source node to said single-poly floating gate with a coupling ratio greater than 90%.

2 more elements

Dependencies are inferred from the claim text.

Single-Polycrystalline Silicon Electrically Erasable and Programmable Memory Device of Varied Gate Oxide Thickness, Using PIP or MIM Coupling Capacitor for Cell Size Reduction and Simultaneous VPP and VNN for Write Voltage Reduction

Life of this patent

Single-Polycrystalline Silicon Electrically Erasable and Programmable Memory Device of Varied Gate Oxide Thickness, Using PIP or MIM Coupling Capacitor for Cell Size Reduction and Simultaneous VPP and VNN for Write Voltage Reduction

Life of this patent

Abstract

Claims90