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US 2011/0235433 A1Published application
Verifying an erase threshold in a memory device
AssigneeMicron Technology, Inc.
InventorAaron Yip
Life of this patent
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Abstract
In one or more embodiments, a memory device is disclosed as having an erase verify operation that includes a negative bias on the p-well in which the memory cell or cells being erased are formed. After an erase pulse is applied to the selected cells to be erased, the p-well is biased with the negative voltage and the erase verify operation is performed to determine the erased state of the cell(s).
Claims20
A method for erase verifying a memory cell, the method comprising:
- biasing a bulk that contains the memory cell with a negative voltage;
- biasing a control gate of the memory cell with a non-negative voltage;
- enabling a selected string of memory cells that includes the memory cell with an enable voltage;
- disabling an unselected string of memory cells with a disable voltage;
- and
- determining a state of the memory cell responsive to an erase current generated at least partially in response to biasing the control gate of the memory cell with the non-negative voltage.
3 more elements
An apparatus comprising:
- a semiconductor comprising a bulk;
- and
- a block of memory cells formed in the bulk wherein, as at least part of an erase verify operation performed with respect to the block, the apparatus is configured to:
- bias the bulk with a negative voltage;
- enable a selected string of the block with an enable voltage;
- and
- disable an unselected string of the block with a disable voltage.
4 more elements
A method for erase verifying memory cells, the method comprising:
- biasing a bulk, in which the memory cells are located, with a negative voltage;
- biasing a word line coupled to the memory cells with an erase verify voltage;
- biasing unselected bit lines with a disable voltage;
- biasing, at a different voltage than the disable voltage, a selected bit line coupled to the memory cells;
- and
- comparing erase currents of each of the memory cells, resulting from the erase verify voltage, with a reference current to determine a state of the memory cells, wherein the erase currents are generated at least partially in response to biasing the word line coupled to the memory cells with the erase verify voltage.
3 more elements
Dependencies are inferred from the claim text.