Apparatus having a string of memory cells
AssigneeMicron Technology, Inc.
InventorsVishal Sarin, Jung-Sheng Hoei, Frankie F. Roohparvar
Life of this patent
Estimating the term…
Abstract
Apparatus having a string of memory cells are useful in semiconductor memory. Some apparatus have circuitry configured to program memory cells of the string in a particular sequence. Some apparatus have circuitry configured to program a threshold voltage of a selected memory cell in the string to match a target voltage compensating, at least in part, for a voltage drop across any unselected memory cells in the string on a source side of the selected memory cell during a sensing operation. Some apparatus have circuitry configured to maintain a resistance presented by source-side unselected memory cells of the string the same between a program verify operation and a later read operation.
Claims20
An apparatus comprising:
- a string of memory cells;
- and
- circuitry configured to program memory cells of the string in a sequence to maintain stability of unselected memory cell resistance presented on a source-side of a given selected memory cell of the string during both verify and read sensing operations.
An apparatus comprising:
- a string of memory cells;
- and
- circuitry configured to program a threshold voltage of a selected memory cell in the string to match a target voltage, wherein the target voltage compensates, at least in part, for a voltage drop across any unselected memory cells in the string on a source side of the selected memory cell during a sensing operation.
An apparatus comprising:
- a string of memory cells;
- and
- circuitry configured to program the string of memory cells sequentially from a memory cell that is adjacent to a line configured to operate as a drain to the string of memory cells during programming, to a memory cell that is adjacent to a line configured to operate as a source to the string of memory cells during programming.
An apparatus comprising:
- a string of memory cells;
- and
- circuitry configured to program the string of memory cells sequentially from a memory cell that is adjacent to a bit line to a memory cell that is adjacent to a source line.
An apparatus comprising:
- a string of p-FET memory cells;
- and
- circuitry configured to program the string of p-FET memory cells sequentially from a memory cell that is adjacent to a source line to a memory cell that is adjacent to a bit line.
An apparatus comprising:
- a string of memory cells;
- and
- circuitry configured to maintain a resistance presented by source-side unselected memory cells of the string the same between a program verify operation and a later read operation.
Dependencies are inferred from the claim text.