Semiconductor memory device for writing data to multiple cells simultaneously and refresh method thereof
AssigneeHynix Semiconductor Inc.
InventorsHEE BOK KANG, SUK KYOUNG HONG
Life of this patent
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Abstract
A semiconductor memory device includes a read/write bit line configured to supply a cell driving voltage. A selecting unit is connected to the read/write bit line and is controlled by a word line. A plurality of cells are connected between the selecting unit and a source line, and the cells are configured to read and write data according to a cell driving voltage. Each switching element of a plurality of switching elements are connected in parallel with a single cell of the plurality of cells, and the plurality of switching elements are controlled selectively by a plurality of bit lines.
Claims14
1-12. (canceled)
A semiconductor memory device comprising:
- a cell array comprising a phase change resistance cell configured to read and write data;
- a register configured to store information of the cell array;
- and
- a refresh control means configured to perform a refresh operation with a specific refresh cycle using the information stored in the register, and to improve a retention characteristic of data stored in the cell array.
A semiconductor memory device comprising:
- a cell array comprising a phase change resistance cell, the phase change resistance cell configured to read and write data;
- and
- a refresh control means configured to perform a refresh operation with a specific refresh cycle according to information stored in the register so as to improve a retention characteristic of data stored in the cell array, wherein the cell array comprises
- a read/write bit line configured to supply a cell driving voltage;
- a selecting unit connected to the read/write bit line and controlled by a word line;
- a plurality of phase change resistance cells connected between the selecting unit and a source line and configured to read/write data according to the cell driving voltage;
- and
- a plurality of switching elements connected in parallel to the plurality of phase change resistance cells and controlled selectively by a plurality of bit lines.
A refresh method of a semiconductor memory device, the method comprising the steps of:
- reading and writing data in a cell array, the cell array comprising a phase change resistor configured to store data corresponding to resistance change, wherein the resistance change corresponds to a change in crystallization state of the phase change resistor that depends on currents applied to the phase change resistor through a bit line;
- and
- refreshing data of the cell array with a specific predetermined refresh cycle so as to improve retention characteristics of data stored in the cell array.
Dependencies are inferred from the claim text.