Semiconductor memory device
AssigneeHitachi, Ltd.
InventorsHiroyuki MINEMURA, Yumiko Anzai, Takahiro Morikawa, Toshimichi Shintani, Yoshitaka Sasago
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Abstract
For decreasing a recording current and suppressing a cross erase simultaneously, a three-dimensional phase-change memory for attaining higher sensitivity and higher reliability by the provision of a chalcogenide type interface layer is provided, in which an electric resistivity, a thermal conductivity, and a melting point of the material of the interface layer are selected appropriately, thereby improving the current concentration to the phase-change material and thermal and material insulation property with Si channel upon writing.
Claims14
A semiconductor memory device comprising:
- a stack in which a plurality of inter-gate insulating layers and a plurality of gate layers are stacked alternately,
- a channel layer formed along the lateral side of the stack,
- an interface layer formed along the lateral side of the channel layer, and
- a phase-change material layer formed along the lateral side of the interface layer,
- wherein the thermal conductivity of the interface layer is lower than the thermal conductivity of the channel layer, and
- wherein the electric resistivity of the interface layer is higher than the electric resistivity of the phase-change material layer in the crystalline state.
A semiconductor memory device comprising:
- a phase-change material layer at a thickness of less than 4 nm;
- and
- an interface layer comprising one of alloy systems of Si and chalcogenide, a material system in which an oxide thereof forms a compound at the boundary relative to the phase-change material layer and oxygen of the oxide is substituted by Te, a metal oxide having an interfacial energy of 3 mJ/m2 or less, and a metal nitride having an interfacial energy 3 mJ/m2 or less.
A semiconductor memory device comprising:
- a cell array including:
- a stack in which a plurality of inter-gate layer insulating layers and a plurality of gate layers are stacked alternately;
- a channel layer formed along the lateral side of the stack;
- and
- a phase-change material layer formed along the lateral side of the channel layer;
- and
- a device controller that controls the voltage for each of the plurality of gate layers and supplies a current flowing by way of the channel layer to the phase-change material layer situated on the lateral side of each of the plurality of gate layers, thereby writing information,
- wherein the device controller writes data successively from the upstream in the moving direction of the carriers in the channel portion.
Dependencies are inferred from the claim text.