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AssigneesQUALCOMM Incorporated, Industry-Academic Cooperation Foundation, Yonsei University
InventorsSeong-Ook Jung, Hyunkook Park, Seung-Chul Song, Mohamed Hassan Abu-Rahma, Lixin Ge, Zhongze Wang, Beom-Mo Han
Estimating the term…
A 5 Transistor Static Random Access Memory (5T SRAM) is designed for reduced cell size and immunity to process variation. The 5T SRAM includes a storage element for storing data, wherein the storage element is coupled to a first voltage and a ground voltage. The storage element can include symmetrically sized cross-coupled inverters. A single access transistor controls read and write operations on the storage element. Control logic is configured to generate a value of the first voltage a write operation that is different from the value of the first voltage for a read operation.
A Static Random Access Memory (SRAM) comprising:
A method in a Static Random Access Memory (SRAM) comprising:
A Static Random Access Memory (SRAM) comprising:
A method in a Static Random Access Memory (SRAM) comprising:
Dependencies are inferred from the claim text.