US 2011/0235397 A1Published application

Non-volatile semiconductor memory device

AssigneeKabushiki Kaisha Toshiba

InventorsTakahiko SASAKI, Mizuki Uda

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Abstract

A memory cell array includes a memory cell having a variable resistance element and disposed between first and second wirings. A control circuit provides a selected first wiring with a first voltage and provide a selected second wiring with a second voltage having a lower voltage value than the first voltage. A current limitation circuit controls a cell current below a first current. It includes a first current generation circuit for storing a cell current at a first point of time and generating a first current of α times the stored cell current. It also includes a second current generation circuit for generating a second current of (β/α) times the cell current at a second point of time. A determination circuit outputs a control signal when the second current exceeds the stored current. The first current generation circuit newly stores a stored current according to the control signal.

Claims20

Dependent claims

A non-volatile semiconductor memory device comprising:

a memory cell array including memory cells, the memory cells each including a variable resistance element and disposed between a plurality of first wirings and a plurality of second wirings, respectively;
a column decoder configured to select any one of the first wirings;
a row decoder configured to select any one of the second wirings;
a control circuit configured to provide selected one of the first wirings with a first voltage and provide selected one of the second wirings with a second voltage having a lower voltage value than the first voltage so as to apply a certain potential difference to a selected memory cell disposed between one of the first wirings selected by the column decoder and one of the second wirings selected by the row decoder, and
a current limitation circuit configured to control a cell current flowing through the selected memory cell not to exceed a first current,
the current limitation circuit comprising:
a first current generation circuit configured to store a cell current at a first point of time as a stored current and generating a first current having a current value of a times the current value of the stored current;
a second current generation circuit configured to generate a second current having a current value of (β/α) (α>β) times the current value of a cell current at a second point of time after the first point of time;
and
a determination circuit for outputting a control signal when it is determined that the current value of the second current exceeds the current value of the stored current,
the first current generation circuit newly storing a stored current at a timing according to the control signal.

8 more elements

A non-volatile semiconductor memory device comprising:

a memory cell array including memory cells, the memory cells each including a variable resistance element and disposed between a plurality of first wirings and a plurality of second wirings, respectively;
a control circuit configured to provide the memory cell with a voltage necessary for a forming operation of the memory cell via the first and the second wirings;
and
a current limitation circuit connected to the first wiring, the current limitation circuit configured to limit a cell current flowing through the memory cell to a certain limit value in the forming operation,
the current limitation circuit generating a first current a certain number times as large as the cell current at a certain point of time, the current limitation circuit controlling a cell current to not more than the first current.

2 more elements

Dependencies are inferred from the claim text.