US 2011/0235394 A1Published application

Semiconductor memory device

AssigneeKabushiki Kaisha Toshiba

InventorsTakahiko Sasaki, Tomonori Kurosawa

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Abstract

A control circuit applies a first voltage to selected one of first lines and applies a second voltage having a voltage value smaller than that of the first voltage to selected one of second lines, such that a certain potential difference is applied across a memory cell disposed at an intersection of the selected one of the first lines and the selected one of the second lines. A current limiting circuit sets a compliance current defining an upper limit of a cell current flowing in the memory cell, and controls such that the cell current flowing in the memory cell does not exceed the compliance current. The current limiting circuit comprises a current generating circuit and a first current mirror circuit. The current generating circuit generates a first current having a current value equal to a current value of the cell current at a certain timing multiplied by a certain constant. The first current mirror circuit mirrors the first current to a current path supplying the first voltage to the first lines.

Claims20

Dependent claims

A semiconductor memory device, comprising:

a memory cell array having memory cells disposed at intersections of a plurality of first lines and a plurality of second lines, each of the memory cells being includes by a rectifier and a variable resistor connected in series;
a control circuit configured to apply a first voltage to selected one of the first lines and to apply a second voltage having a voltage value smaller than that of the first voltage to selected one of the second lines, such that a certain potential difference is applied across the memory cell disposed at the intersection of the selected one of the first lines and the selected one of the second lines;
and
a current limiting circuit configured to set a compliance current defining an upper limit of a cell current flowing in the memory cell, and to perform a control such that the cell current flowing in the memory cell does not exceed the compliance current,
the current limiting circuit comprising:
a current generating circuit configured to generate a first current having a current value equal to a current value of the cell current at a certain timing multiplied by a certain constant;
and
a first current mirror circuit configured to mirror the first current to a current path supplying the first voltage to the first lines.

5 more elements

A semiconductor memory device, comprising:

a memory cell array having memory cells disposed at intersections of a plurality of first lines and a plurality of second lines, each of the memory cells including a variable resistor;
and
a control circuit configured to apply a certain voltage to selected one of the first lines and to selected one of the second lines, and thereby apply a voltage to the memory cell disposed at the intersection of the selected one of the first lines and the selected one of the second lines,
in a forming operation for rendering the memory cell in a state where transition is possible between a high-resistance state and a low-resistance state, the control circuit repeatedly executing a first processing and a second processing based on a first cell current flowing in the memory cell when a first voltage is applied to the memory cell,
the first processing being an operation of raising the first voltage by a certain amount if the first cell current is judged not to have reached a limiting current, and
the second processing being an operation of raising the limiting current and lower the first voltage to an initial value if the first cell current is judged to have reached the limiting current.

3 more elements

Dependencies are inferred from the claim text.