Reference Cell Write Operations At A Memory

A non-volatile memory comprising:

• a plurality of memory cells;
• first write circuitry to write a logic one value to a first reference cell, the first reference cell comprising a first resistance based memory element;
• second write circuitry to write a logic zero value to a second reference cell, the second reference cell comprising a second resistance based memory element;
• a column decode circuit;
• and
• a row decode circuit;
• wherein each of the reference cells is selectable for a write operation based on a first output of the row decode circuit and on a second output of the column decode circuit and is programmable concurrently with a write operation of one of the plurality of the memory cells in response to receiving a write command without requiring a dedicated reference cell write command.

An apparatus comprising:

• a memory comprising:
• means for selecting a reference circuit for a write operation based on a first output of a row decode circuit and a second output of a column decode circuit;
• and
• means for programming the reference circuit concurrently with a write operation of at least one of a plurality of memory cells in a memory array in response to receiving a write command and without requiring a dedicated reference circuit write command.

A method comprising:

• receiving design information representing at least one physical property of a semiconductor device, the semiconductor device comprising:
• a memory array comprising a plurality of memory cells and reference lines, at least one of the reference lines associated with a reference cell that is programmable concurrently with a write operation of one of the plurality of the memory cells in the memory array in response to receiving a write command without requiring a dedicated reference cell write command;
• transforming the design information to comply with a file format;
• and
• generating a data file comprising the transformed design information.

A method comprising:

• receiving a data file comprising design information corresponding to a semiconductor device;
• and
• fabricating the semiconductor device according to the design information, wherein the semiconductor device comprises:
• a memory array comprising a plurality of memory cells and reference lines, at least one of the reference lines associated with a reference cell that is programmable concurrently with a write operation of one of the plurality of the memory cells in the memory array in response to receiving a write command and without requiring a dedicated reference cell write command.

A method comprising:

• receiving design information comprising physical positioning information of a packaged semiconductor device on a circuit board, the packaged semiconductor device comprising a semiconductor memory comprising:
• a memory array comprising a plurality of memory cells and reference lines, at least one of the reference lines associated with a reference cell that is programmable concurrently with a write operation of one of the plurality of the memory cells in the memory array in response to receiving a write command and without requiring a dedicated reference cell write command;
• and
• transforming the design information to generate a data file.

A method comprising:

• receiving a data file comprising design information comprising physical positioning information of a packaged semiconductor device on a circuit board;
• and
• manufacturing the circuit board configured to receive the packaged semiconductor device according to the design information, wherein the packaged semiconductor device comprises a structure comprising:
• a memory array comprising a plurality of memory cells and reference lines, at least one of the reference lines associated with a reference cell that is programmable concurrently with a write operation of one of the plurality of the memory cells in the memory array in response to receiving a write command and without requiring a dedicated reference cell write command.